115 static uint8_t g_spi_axi_pos = 0u;
148     for (slave = 0u; slave < (uint16_t)MSS_SPI_MAX_NB_OF_SLAVES; slave++)  in MSS_SPI_init()
220     this_spi->hw_reg->FRAMESUP = 0u;  in MSS_SPI_configure_slave_mode()
253     ASSERT(0u == (clk_div & 0x00000001U));  in MSS_SPI_configure_master_mode()
406     this_spi->hw_reg->FRAMESUP = 0u;  in MSS_SPI_transfer_frame()
419     while (0u == tx_done)  in MSS_SPI_transfer_frame()
427     while (0u == rx_ready)  in MSS_SPI_transfer_frame()
449     uint32_t transfer_idx = 0u;  in MSS_SPI_transfer_block()
454     uint32_t transit = 0u;  in MSS_SPI_transfer_block()
472     if (0u == transfer_size)  in MSS_SPI_transfer_block()
504     while (0u == rx_fifo_empty)  in MSS_SPI_transfer_block()
509     tx_idx = 0u;  in MSS_SPI_transfer_block()
510     rx_idx = 0u;  in MSS_SPI_transfer_block()
533         if (0u == rx_fifo_empty)  in MSS_SPI_transfer_block()
549         if (0u == tx_fifo_full)  in MSS_SPI_transfer_block()
596     this_spi->block_rx_handler = 0u;  in MSS_SPI_set_frame_rx_handler()
597     this_spi->cmd_handler = 0u;  in MSS_SPI_set_frame_rx_handler()
613     this_spi->hw_reg->FRAMESUP = 0u;  in MSS_SPI_set_frame_rx_handler()
660     this_spi->block_rx_handler = 0u;  in MSS_SPI_set_slave_tx_frame()
661     this_spi->cmd_handler = 0u;  in MSS_SPI_set_slave_tx_frame()
665     this_spi->slave_tx_buffer = 0u;  in MSS_SPI_set_slave_tx_frame()
666     this_spi->slave_tx_size = 0u;  in MSS_SPI_set_slave_tx_frame()
667     this_spi->slave_tx_idx = 0u;  in MSS_SPI_set_slave_tx_frame()
681     this_spi->hw_reg->FRAMESUP = 0u;  in MSS_SPI_set_slave_tx_frame()
726     uint32_t done = 0u;  in MSS_SPI_set_slave_block_buffers()
746         this_spi->cmd_done = 0u;  in MSS_SPI_set_slave_block_buffers()
751     this_spi->frame_rx_handler = 0u;  in MSS_SPI_set_slave_block_buffers()
758     this_spi->slave_rx_idx = 0u;  in MSS_SPI_set_slave_block_buffers()
763     this_spi->slave_tx_idx = 0u;  in MSS_SPI_set_slave_block_buffers()
771     if (0u != (this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK))  in MSS_SPI_set_slave_block_buffers()
777     while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in MSS_SPI_set_slave_block_buffers()
795     while ((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK))  in MSS_SPI_set_slave_block_buffers()
796             && (0u == done))  in MSS_SPI_set_slave_block_buffers()
803         else if (0u != this_spi->cmd_done)  in MSS_SPI_set_slave_block_buffers()
816     if (tx_buff_size > 0u)  in MSS_SPI_set_slave_block_buffers()
871     this_spi->resp_tx_buffer   = 0u;  in MSS_SPI_set_cmd_handler()
872     this_spi->resp_buff_size   = 0u;  in MSS_SPI_set_cmd_handler()
873     this_spi->resp_buff_tx_idx = 0u;  in MSS_SPI_set_cmd_handler()
882         this_spi->cmd_handler = 0u;  in MSS_SPI_set_cmd_handler()
883         this_spi->hw_reg->CMDSIZE = 0u;  in MSS_SPI_set_cmd_handler()
890         this_spi->cmd_done = 0u;  in MSS_SPI_set_cmd_handler()
902         this_spi->slave_tx_idx    = 0u;  in MSS_SPI_set_cmd_handler()
927     this_spi->resp_buff_tx_idx = 0u;  in MSS_SPI_set_cmd_response()
994     uint32_t guard = 0u;  in fill_slave_tx_fifo()
996     while ((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&  in fill_slave_tx_fifo()
1007         while ((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&  in fill_slave_tx_fifo()
1017     if ((0u != this_spi->cmd_done) &&  in fill_slave_tx_fifo()
1021         while ((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&  in fill_slave_tx_fifo()
1048         while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in read_slave_rx_fifo()
1062         while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in read_slave_rx_fifo()
1076         while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in read_slave_rx_fifo()
1097     if (0u != (*this_mis & RXDONE_IRQ_MASK))  in mss_spi_isr()
1102             while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in mss_spi_isr()
1115             while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in mss_spi_isr()
1131             while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in mss_spi_isr()
1140     if (0u != (*this_mis & TXDONE_IRQ_MASK))  in mss_spi_isr()
1156     if (0u != (*this_mis & CMD_IRQ_MASK))  in mss_spi_isr()
1178     if (0u != (*this_mis & RXOVFLOW_IRQ_MASK))  in mss_spi_isr()
1193     if (0u != (*this_mis & TXURUN_IRQ_MASK))  in mss_spi_isr()
1198             this_spi->hw_reg->FRAMESUP = 0u;  in mss_spi_isr()
1209             this_spi->slave_tx_idx = 0u;  in mss_spi_isr()
1222     if (0u != (*this_mis & SSEND_IRQ_MASK))  in mss_spi_isr()
1234             this_spi->cmd_done = 0u;  in mss_spi_isr()
1235             this_spi->resp_tx_buffer = 0u;  in mss_spi_isr()
1236             this_spi->resp_buff_size = 0u;  in mss_spi_isr()
1237             this_spi->resp_buff_tx_idx = 0u;  in mss_spi_isr()
1245         this_spi->slave_tx_idx = 0u;  in mss_spi_isr()
1252         this_spi->slave_rx_idx = 0u;  in mss_spi_isr()
1327         this_spi->buffer_overflow_handler(0u);  in recover_from_rx_overflow()