Searched refs:SYSREG (Results 1 – 14 of 14) sorted by relevance
228 config_32_copy((void *)(&(SYSREG->IOMUX0_CR)), in io_mux_and_bank_config()260 config_32_copy((void *)(&(SYSREG->MSSIO_BANK4_IO_CFG_0_1_CR)), in io_mux_and_bank_config()264 config_32_copy((void *)(&(SYSREG->MSSIO_BANK2_IO_CFG_0_1_CR)), in io_mux_and_bank_config()296 config_32_copy((void *)(&(SYSREG->IOMUX0_CR)), in io_mux_and_bank_config_alt()328 config_32_copy((void *)(&(SYSREG->MSSIO_BANK4_IO_CFG_0_1_CR)), in io_mux_and_bank_config_alt()332 config_32_copy((void *)(&(SYSREG->MSSIO_BANK2_IO_CFG_0_1_CR)), in io_mux_and_bank_config_alt()588 SYSREG->TEMP0 = 0x11111111; in gpio_toggle_test()594 SYSREG->TEMP0 = 0x12345678; in gpio_toggle_test()599 SYSREG->TEMP0 = 0x12345678; in gpio_toggle_test()602 SYSREG->TEMP0 = 0xFFFFFFFFUL; in gpio_toggle_test()[all …]
83 SYSREG->RTC_CLOCK_CR &= ~(0x01U<<16); /* disable RTC clock */ in set_RTC_divisor()85 SYSREG->RTC_CLOCK_CR = (LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK / \ in set_RTC_divisor()88 SYSREG->RTC_CLOCK_CR |= (0x01U<<16); /* enable RTC clock */ in set_RTC_divisor()231 SYSREG->ENVM_CR = LIBERO_SETTING_MSS_ENVM_CR; in mss_mux_post_mss_pll_config()242 while ((SYSREG->ENVM_CR & ENVM_CR_CLOCK_OKAY_MASK) !=\ in mss_mux_post_mss_pll_config()269 SYSREG->CLOCK_CONFIG_CR = LIBERO_SETTING_MSS_CLOCK_CONFIG_CR; in mss_mux_post_mss_pll_config()
74 SYSREG->TEMP0 = (0U << 16U) | (3U << 8U) | 3U; in mss_nwc_init()75 SYSREG->TEMP0 = 0x44444444U; in mss_nwc_init()130 SYSREG->DFIAPB_CR = 0x00000001U; in mss_nwc_init()
67 #define SIM_FEEDBACK0(x) (SYSREG->TEMP0 = (uint32_t)x)68 #define SIM_FEEDBACK1(x) (SYSREG->TEMP1 = (uint32_t)x)
95 SYSREG->SUBBLK_CLOCK_CR |= (SUBBLK_CLOCK_CR_MMUART0_MASK); in setup_ddr_debug_port()97 SYSREG->SOFT_RESET_CR &= (uint32_t)(~SUBBLK_CLOCK_CR_MMUART0_MASK); in setup_ddr_debug_port()
712 SYSREG->SOFT_RESET_CR &= 0x00U; in ddr_setup()713 SYSREG->SUBBLK_CLOCK_CR = 0xffffffffUL; in ddr_setup()714 SYSREG->GPIO_INTERRUPT_FAB_CR = 0x00000000UL; in ddr_setup()857 SYSREG->SUBBLK_CLOCK_CR |= SUBBLK_CLOCK_CR_DDRC_MASK; in ddr_setup()859 SYSREG->SOFT_RESET_CR &= (uint32_t)~SOFT_RESET_CR_DDRC_MASK; in ddr_setup()
126 SYSREG->SUBBLK_CLOCK_CR &= (uint32_t)~(peripheral_mask); in peripheral_on_off()128 SYSREG->SOFT_RESET_CR |= (uint32_t)(peripheral_mask); in peripheral_on_off()133 SYSREG->SUBBLK_CLOCK_CR |= (peripheral_mask); in peripheral_on_off()135 SYSREG->SOFT_RESET_CR &= (uint32_t)~(peripheral_mask); in peripheral_on_off()
59 SYSREG->L2_SHUTDOWN_CR = LIBERO_SETTING_L2_SHUTDOWN_CR; in config_l2_cache()
4063 #define SYSREG ((volatile mss_sysreg_t * const) BASE32_ADDR_MSS_SYSREG) macro
573 SYSREG->APBBUS_CR = reg_value; in mss_set_apb_bus_cr()583 return (SYSREG->APBBUS_CR); in mss_get_apb_bus_cr()
196 SYSREG->SUBBLK_CLOCK_CR |= (uint32_t)2U; in MSS_MAC_init()198 SYSREG->SOFT_RESET_CR |= (uint32_t)2U; in MSS_MAC_init()209 SYSREG->SOFT_RESET_CR &= (uint32_t)~2U; in MSS_MAC_init()214 SYSREG->SUBBLK_CLOCK_CR |= (uint32_t)4U; in MSS_MAC_init()216 SYSREG->SOFT_RESET_CR |= (uint32_t)4U; in MSS_MAC_init()227 SYSREG->SOFT_RESET_CR &= (uint32_t)~4U; in MSS_MAC_init()5438 SYSREG->MAC_CR = (SYSREG->MAC_CR & ~MAC_CONFIG_SPEED_MASK) | link_speed;5525 SYSREG->APBBUS_CR &= ~MSS_MAC_GEM0_ABP_BIT; in instances_init()5532 SYSREG->APBBUS_CR |= MSS_MAC_GEM0_ABP_BIT; in instances_init()5571 SYSREG->APBBUS_CR &= ~MSS_MAC_GEM1_ABP_BIT; in instances_init()[all …]
747 SYSREG->MAC_CR = (SYSREG->MAC_CR & ~MAC_CONFIG_SPEED_MASK) | link_speed; in MSS_MAC_VSC8575_phy_autonegotiate()
172 SYSREG->SOFT_RESET_CR |= SYSREG_CAN_SOFTRESET_MASK; in MSS_CAN_set_mode()173 SYSREG->SOFT_RESET_CR &= ~SYSREG_CAN_SOFTRESET_MASK; in MSS_CAN_set_mode()
311 SYSREG->SOFT_RESET_CR &= ~(MMC_SET << MMC_SOFTWARE_RESET_SHIFT); in MSS_MMC_init()
