Lines Matching refs:SYSREG
228 config_32_copy((void *)(&(SYSREG->IOMUX0_CR)), in io_mux_and_bank_config()
260 config_32_copy((void *)(&(SYSREG->MSSIO_BANK4_IO_CFG_0_1_CR)), in io_mux_and_bank_config()
264 config_32_copy((void *)(&(SYSREG->MSSIO_BANK2_IO_CFG_0_1_CR)), in io_mux_and_bank_config()
296 config_32_copy((void *)(&(SYSREG->IOMUX0_CR)), in io_mux_and_bank_config_alt()
328 config_32_copy((void *)(&(SYSREG->MSSIO_BANK4_IO_CFG_0_1_CR)), in io_mux_and_bank_config_alt()
332 config_32_copy((void *)(&(SYSREG->MSSIO_BANK2_IO_CFG_0_1_CR)), in io_mux_and_bank_config_alt()
588 SYSREG->TEMP0 = 0x11111111; in gpio_toggle_test()
594 SYSREG->TEMP0 = 0x12345678; in gpio_toggle_test()
599 SYSREG->TEMP0 = 0x12345678; in gpio_toggle_test()
602 SYSREG->TEMP0 = 0xFFFFFFFFUL; in gpio_toggle_test()
605 SYSREG->TEMP0 = 0x12345678; in gpio_toggle_test()
610 SYSREG->TEMP0 = 0x12345678; in gpio_toggle_test()
624 SYSREG->SOFT_RESET_CR &= ~((1U<<20U)|(1U<<21U)|(1U<<22U)); in gpio_set_config()
625 SYSREG->SUBBLK_CLOCK_CR |= ((1U<<20U)|(1U<<21U)|(1U<<22U)); in gpio_set_config()