Home
last modified time | relevance | path

Searched refs:STATUS (Results 1 – 25 of 57) sorted by relevance

123

/hal_microchip-latest/mec5/drivers/
Dmec_bclink.c65 base->STATUS = MEC_BIT(MEC_BCL_STATUS_SRST_Pos) | MEC_BIT(MEC_BCL_STATUS_BCERR_Pos); in mec_hal_bcl_init()
73 base->STATUS &= (uint32_t)~MEC_BIT(MEC_BCL_STATUS_SRST_Pos); in mec_hal_bcl_init()
87 regs->STATUS |= MEC_BIT(MEC_BCL_STATUS_SRST_Pos); in mec_hal_bcl_soft_reset()
89 regs->STATUS = (uint32_t)~MEC_BIT(MEC_BCL_STATUS_SRST_Pos); in mec_hal_bcl_soft_reset()
121 if (regs->STATUS & MEC_BIT(MEC_BCL_STATUS_BUSY_Pos)) { in mec_hal_bcl_is_busy()
165 if (regs->STATUS & MEC_BIT(MEC_BCL_STATUS_BCERR_Pos)) { in mec_hal_bcl_is_error()
180 regs->STATUS |= MEC_BIT(MEC_BCL_STATUS_BCERR_Pos); in mec_hal_bcl_clear_error()
233 regs->STATUS = (regs->STATUS & (uint32_t)~regmsk) | ien; in mec_hal_bcl_intr_ctrl()
305 if (regs->STATUS & MEC_BIT(MEC_BCL_STATUS_BUSY_Pos)) { in mec_hal_bcl_start()
309 regs->STATUS |= MEC_BIT(MEC_BCL_STATUS_BCERR_Pos); in mec_hal_bcl_start()
[all …]
Dmec_wdt.c48 regs->STATUS = UINT32_MAX; in mec_hal_wdt_init()
111 return (uint8_t)(regs->STATUS & 0xffu); in mec_hal_wdt_intr_get_status()
116 regs->STATUS = MEC_BIT(MEC_WDT_STATUS_ISTATUS_Pos); in mec_hal_wdt_intr_clear_status()
134 regs->STATUS = MEC_BIT(MEC_WDT_STATUS_ISTATUS_Pos); in mec_hal_wdt_intr_helper()
Dmec_eeprom.c44 regs->STATUS = UINT32_MAX; in mec_hal_eeprom_init()
116 return regs->STATUS; in mec_hal_eeprom_status()
125 regs->STATUS = clrmsk; in mec_hal_eeprom_status_clr()
136 if (regs->STATUS & MEC_BIT(MEC_EEPROM_CTRL_STATUS_XFR_ACTIVE_Pos)) { in mec_hal_eeprom_is_busy()
Dmec_qspi.c248 base->STATUS = UINT32_MAX; in qspi_intr_clr_dis()
606 while (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_ACTIVE_Pos)) { in mec_hal_qspi_force_stop()
624 qsts = base->STATUS; in mec_hal_qspi_done()
643 return base->STATUS; in mec_hal_qspi_hw_status()
652 base->STATUS = msk; in mec_hal_qspi_hw_status_clr()
701 if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_TXBE_Pos)) { in mec_hal_qspi_tx_fifo_is_empty()
712 if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_TXBF_Pos)) { in mec_hal_qspi_tx_fifo_is_full()
723 if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_RXBE_Pos)) { in mec_hal_qspi_rx_fifo_is_empty()
734 if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_RXBF_Pos)) { in mec_hal_qspi_rx_fifo_is_full()
748 base->STATUS = UINT32_MAX; in mec_hal_qspi_start()
[all …]
Dmec_tach.c66 regs->STATUS = UINT32_MAX; in mec_hal_tach_init()
155 return regs->STATUS; in mec_hal_tach_status()
160 regs->STATUS = status; in mec_hal_tach_status_clr()
Dmec_adc.c257 return regs->STATUS; in mec_hal_adc_channels_done()
288 regs->STATUS |= regs->SCHEN; in mec_hal_adc_status_clear()
294 regs->STATUS |= regs->RCHEN; in mec_hal_adc_status_clear()
329 regs->STATUS = single_chan_bm | rpt_chan_bm; in mec_hal_adc_start()
Dmec_ps2.c74 regs->STATUS = regs->RTXB | (MEC_BIT(MEC_PS2_STATUS_RXTMO_Pos) in ps2_clear_all_status()
270 return regs->STATUS; in mec_hal_ps2_get_status()
275 regs->STATUS = (uint8_t)(clrmsk & 0xffu); in mec_hal_ps2_clr_status()
/hal_microchip-latest/mpfs/drivers/mss/mss_qspi/
Dmss_qspi.c111 while ((QSPI->STATUS & STTS_READY_MASK) == 0u){}; in MSS_QSPI_polled_transfer_block()
133 while (QSPI->STATUS & STTS_TFFULL_MASK){}; in MSS_QSPI_polled_transfer_block()
142 while (QSPI->STATUS & STTS_TFFULL_MASK){}; in MSS_QSPI_polled_transfer_block()
158 while (QSPI->STATUS & STTS_RFEMPTY_MASK){}; in MSS_QSPI_polled_transfer_block()
167 while (QSPI->STATUS & STTS_RFEMPTY_MASK){}; in MSS_QSPI_polled_transfer_block()
171 while (0u == (QSPI->STATUS & STTS_RDONE_MASK)) in MSS_QSPI_polled_transfer_block()
173 skips = (uint64_t)((QSPI->STATUS & STTS_FLAGSX4_MASK) ? in MSS_QSPI_polled_transfer_block()
205 if ((QSPI->STATUS & STTS_READY_MASK) == 0u) in MSS_QSPI_irq_transfer_block()
246 while (QSPI->STATUS & STTS_TFFULL_MASK){}; in MSS_QSPI_irq_transfer_block()
255 while (QSPI->STATUS & STTS_TFFULL_MASK){}; in MSS_QSPI_irq_transfer_block()
[all …]
Dmss_qspi.h372 volatile uint32_t STATUS; member
734 return(QSPI->STATUS); in MSS_QSPI_read_status()
/hal_microchip-latest/mpfs/drivers/mss/mss_watchdog/
Dmss_watchdog.h282 volatile uint32_t STATUS; member
491 return ((wdog_hw_base[wd_num]->STATUS & MSS_WDOG_FORBIDDEN_MASK) >> in MSS_WD_forbidden_status()
620 wdog_hw_base[wd_num]->STATUS |= MSS_WDOG_WDOG_TRIPPED_MASK; in MSS_WD_clear_timeout_irq()
630 wdog_hw_base[wd_num]->STATUS |= MSS_WDOG_WDOG_TRIPPED_MASK; in MSS_WD_clear_timeout_irq()
659 wdog_hw_base[wd_num]->STATUS |= MSS_WDOG_MVRP_TRIPPED_MASK; in MSS_WD_clear_mvrp_irq()
669 wdog_hw_base[wd_num]->STATUS |= MSS_WDOG_MVRP_TRIPPED_MASK; in MSS_WD_clear_mvrp_irq()
711 return((wdog_hw_base[wd_num]->STATUS & MSS_WDOG_TRIGGERED_MASK) >> in MSS_WD_timeout_occured()
735 (uint32_t)(wdog_hw_base[wd_num]->STATUS | in MSS_WD_force_reset()
Dmss_watchdog.c76 if (!(MSS_WDOG_FORBIDDEN_MASK & wdog_hw_base[wd_num]->STATUS)) in MSS_WD_configure()
/hal_microchip-latest/mpfs/drivers/mss/mss_spi/
Dmss_spi.c331 rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK; in MSS_SPI_set_slave_select()
375 rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK; in MSS_SPI_clear_slave_select()
418 tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK; in MSS_SPI_transfer_frame()
421 tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK; in MSS_SPI_transfer_frame()
426 rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK; in MSS_SPI_transfer_frame()
429 rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK; in MSS_SPI_transfer_frame()
486 rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK; in MSS_SPI_transfer_block()
503 rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK; in MSS_SPI_transfer_block()
507 rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK; in MSS_SPI_transfer_block()
532 rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK; in MSS_SPI_transfer_block()
[all …]
/hal_microchip-latest/mec5/
DCMakeLists.txt8 message(STATUS "HAL mec5 SoC series: MEC5_SERIES = ${MEC5_SERIES}")
9 message(STATUS "HAL mec5 SoC device: MEC5_DEVICE = ${MEC5_DEVICE}")
/hal_microchip-latest/pic32c/pic32cxsg/include/fixups/component/
Dtc_component_fixup_pic32cxsg.h223 uint32_t STATUS:1; /*!< bit: 3 STATUS */ member
359 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member
385 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member
409 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ member
Dramecc_component_fixup_pic32cxsg.h86 __I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */ member
Dpdec_component_fixup_pic32cxsg.h207 uint32_t STATUS:1; /*!< bit: 3 Status Synchronization Busy */ member
309 __IO PDEC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/W 16) Status */ member
/hal_microchip-latest/mpfs/mpfs_hal/common/
Dmss_mpu.h114 __IO MPU_FailStatus_TypeDef STATUS; member
198 return (MSS_MPU(master_port)->STATUS); in MSS_MPU_get_failstatus()
/hal_microchip-latest/mec5/devices/common/
Dmec5_bcl_v1.h18 …__IOM uint32_t STATUS; /*!< (@ 0x00000000) BC-Link status … member
Dmec5_wdt_v2.h22 …__IOM uint32_t STATUS; /*!< (@ 0x00000010) WDT Status … member
Dmec5_tach_v1.h19 …__IOM uint32_t STATUS; /*!< (@ 0x00000004) Tachometer status … member
Dmec5_btmr_v1.h20 …__IOM uint32_t STATUS; /*!< (@ 0x00000008) Basic timer status … member
Dmec5_ps2_v1.h22 …__IOM uint8_t STATUS; /*!< (@ 0x00000008) PS2 status … member
Dmec5_eeprom_ctrl_v1.h20 …__IOM uint32_t STATUS; /*!< (@ 0x00000008) Controller status register … member
Dmec5_gspi_v1.h20 …__IM uint32_t STATUS; /*!< (@ 0x00000008) GSPI status … member
/hal_microchip-latest/mec/mec1501/component/
Dport80cap.h143 __IOM uint32_t STATUS; /*!< (@ 0x0108) Status. Read-only */ member

123