331     rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK;  in MSS_SPI_set_slave_select()
375     rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK;  in MSS_SPI_clear_slave_select()
418     tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;  in MSS_SPI_transfer_frame()
421         tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;  in MSS_SPI_transfer_frame()
426     rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK;  in MSS_SPI_transfer_frame()
429         rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK;  in MSS_SPI_transfer_frame()
486     rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK;  in MSS_SPI_transfer_block()
503     rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;  in MSS_SPI_transfer_block()
507         rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;  in MSS_SPI_transfer_block()
532         rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;  in MSS_SPI_transfer_block()
548         tx_fifo_full = this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK;  in MSS_SPI_transfer_block()
606     tx_fifo_empty = this_spi->hw_reg->STATUS & TX_FIFO_EMPTY_MASK;  in MSS_SPI_set_frame_rx_handler()
771     if (0u != (this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK))  in MSS_SPI_set_slave_block_buffers()
777     while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in MSS_SPI_set_slave_block_buffers()
795     while ((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK))  in MSS_SPI_set_slave_block_buffers()
981     tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;  in MSS_SPI_tx_done()
996     while ((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&  in fill_slave_tx_fifo()
1007         while ((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&  in fill_slave_tx_fifo()
1021         while ((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&  in fill_slave_tx_fifo()
1048         while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in read_slave_rx_fifo()
1062         while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in read_slave_rx_fifo()
1076         while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in read_slave_rx_fifo()
1102             while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in mss_spi_isr()
1115             while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in mss_spi_isr()
1131             while (0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))  in mss_spi_isr()