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Searched refs:clock (Results 1 – 25 of 37) sorted by relevance

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/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_clock.c662 static cy_rslt_t _cyhal_clock_set_enabled_unsupported(cyhal_clock_t *clock, bool enabled, bool wait… in _cyhal_clock_set_enabled_unsupported() argument
664 CY_UNUSED_PARAMETER(clock); in _cyhal_clock_set_enabled_unsupported()
670 static cy_rslt_t _cyhal_clock_set_frequency_unsupported(cyhal_clock_t *clock, uint32_t hz, const cy… in _cyhal_clock_set_frequency_unsupported() argument
672 CY_UNUSED_PARAMETER(clock); in _cyhal_clock_set_frequency_unsupported()
678 static cy_rslt_t _cyhal_clock_set_divider_unsupported(cyhal_clock_t *clock, uint32_t divider) in _cyhal_clock_set_divider_unsupported() argument
680 CY_UNUSED_PARAMETER(clock); in _cyhal_clock_set_divider_unsupported()
685 static cy_rslt_t _cyhal_clock_set_source_unsupported(cyhal_clock_t *clock, const cyhal_clock_t *sou… in _cyhal_clock_set_source_unsupported() argument
687 CY_UNUSED_PARAMETER(clock); in _cyhal_clock_set_source_unsupported()
692 static bool _cyhal_clock_is_enabled_true(const cyhal_clock_t *clock) in _cyhal_clock_is_enabled_true() argument
694 CY_UNUSED_PARAMETER(clock); in _cyhal_clock_is_enabled_true()
[all …]
Dcyhal_utils_impl.c140 static inline cy_rslt_t _cyhal_utils_allocate_peri(cyhal_clock_t *clock, uint8_t peri_group, cyhal_… in _cyhal_utils_allocate_peri() argument
167 result = _cyhal_clock_allocate_peri(clock, PERI_DIVIDERS[i]); in _cyhal_utils_allocate_peri()
177 result = _cyhal_clock_allocate_peri(clock, adjusted_div); in _cyhal_utils_allocate_peri()
180 result = cyhal_clock_allocate(clock, PERI_DIVIDERS[i]); in _cyhal_utils_allocate_peri()
195 result = cyhal_clock_reserve(clock, &CYHAL_CLOCK_HF[hfclk_idx]); in _cyhal_utils_allocate_peri()
509 cy_rslt_t _cyhal_utils_allocate_clock(cyhal_clock_t *clock, const cyhal_resource_inst_t *clocked_it… in _cyhal_utils_allocate_clock() argument
548 return _cyhal_utils_allocate_peri(clock, 0, div, accept_larger); in _cyhal_utils_allocate_clock()
552 return cyhal_clock_reserve(clock, &clock_rsc); in _cyhal_utils_allocate_clock()
556 cy_rslt_t _cyhal_utils_allocate_clock(cyhal_clock_t *clock, const cyhal_resource_inst_t *clocked_it… in _cyhal_utils_allocate_clock() argument
579 return _cyhal_utils_allocate_peri(clock, peri_group, div, accept_larger); in _cyhal_utils_allocate_clock()
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Dcyhal_scb_common.c526 static cy_rslt_t _cyhal_scb_configure_peri_clock(cyhal_clock_t *clock, const cyhal_resource_inst_t … in _cyhal_scb_configure_peri_clock() argument
529 …ock_block_t clk_type = (cyhal_clock_block_t)_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block); in _cyhal_scb_configure_peri_clock()
558 result = _cyhal_utils_allocate_clock(clock, resource, PERI_DIVIDERS[i], true); in _cyhal_scb_configure_peri_clock()
567 result = cyhal_clock_set_frequency(clock, freq, &tolerance); in _cyhal_scb_configure_peri_clock()
570 cyhal_clock_free(clock); in _cyhal_scb_configure_peri_clock()
592 … cyhal_clock_t *clock = is_i2c ? &(((cyhal_i2c_t *)obj)->clock) : &(((cyhal_ezi2c_t *)obj)->clock); in _cyhal_i2c_set_peri_divider() local
615 … cy_rslt_t status = _cyhal_scb_configure_peri_clock(clock, resource, peri_freq, is_clock_owned); in _cyhal_i2c_set_peri_divider()
621 _cyhal_scb_get_clock_index(block_num), clock) == CY_SYSCLK_SUCCESS) in _cyhal_i2c_set_peri_divider()
625 status = cyhal_clock_set_enabled(clock, false, false); in _cyhal_i2c_set_peri_divider()
628 status = cyhal_clock_set_frequency(clock, peri_freq, NULL); in _cyhal_i2c_set_peri_divider()
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Dcyhal_usb_dev.c112 static bool _cyhal_usb_dev_set_hf_divider(uint32_t clock, uint32_t input_freq, uint32_t target…
114 static cy_rslt_t _cyhal_usb_dev_init_pll(uint32_t clock, uint32_t pll, uint32_t target_freq);
200 static bool _cyhal_usb_dev_set_hf_divider(uint32_t clock, uint32_t input_freq, uint32_t target_freq) in _cyhal_usb_dev_set_hf_divider() argument
209 Cy_SysClk_ClkHfSetDivider(clock, divider); in _cyhal_usb_dev_set_hf_divider()
240 static cy_rslt_t _cyhal_usb_dev_init_pll(uint32_t clock, uint32_t pll, uint32_t target_freq) in _cyhal_usb_dev_init_pll() argument
245 Cy_SysClk_ClkHfSetSource(clock, (cy_en_clkhf_in_sources_t)(pll)); in _cyhal_usb_dev_init_pll()
260 Cy_SysClk_ClkHfSetDivider(clock, CY_SYSCLK_CLKHF_NO_DIVIDE); in _cyhal_usb_dev_init_pll()
285 uint32_t clock = _CYHAL_USB_DEV_USB_CLK_HF; in _cyhal_usb_dev_hf_clock_setup() local
288 Cy_SysClk_ClkHfDisable(clock); in _cyhal_usb_dev_hf_clock_setup()
301 if (_cyhal_usb_dev_set_hf_divider(clock, clk_pll_freq, _CYHAL_USB_DEV_USB_CLK_HF_FREQ)) in _cyhal_usb_dev_hf_clock_setup()
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Dcyhal_keyscan.c67 … uint8_t num_rows, const cyhal_gpio_t *rows, const cyhal_clock_t *clock);
176 … uint8_t num_rows, const cyhal_gpio_t *rows, const cyhal_clock_t *clock) in _cyhal_keyscan_init_resources() argument
275 if (clock == NULL) in _cyhal_keyscan_init_resources()
282 obj->clock = clock_keyscan; in _cyhal_keyscan_init_resources()
286 else if(clock->block == CYHAL_CLOCK_BLOCK_MF) in _cyhal_keyscan_init_resources()
288 obj->clock = *clock; in _cyhal_keyscan_init_resources()
339 … uint8_t num_rows, const cyhal_gpio_t *rows, const cyhal_clock_t *clock) in cyhal_keyscan_init() argument
346 …cy_rslt_t result = _cyhal_keyscan_init_resources(obj, num_columns, columns, num_rows, rows, clock); in cyhal_keyscan_init()
372 obj->clock = *cfg->clock; in cyhal_keyscan_init_cfg()
413 cyhal_clock_free(&(obj->clock)); in cyhal_keyscan_free()
Dcyhal_timer.c117 obj->tcpwm.clock = *clk; in _cyhal_timer_init_hw()
118 obj->tcpwm.clock_hz = cyhal_clock_get_frequency(&obj->tcpwm.clock); in _cyhal_timer_init_hw()
119 if (CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_assign_divider(pclk, &(obj->tcpwm.clock))) in _cyhal_timer_init_hw()
124 …else if (CY_RSLT_SUCCESS == (result = _cyhal_utils_allocate_clock(&(obj->tcpwm.clock), timer, CYHA… in _cyhal_timer_init_hw()
135 … if (CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_assign_divider(pclk, &(obj->tcpwm.clock))) in _cyhal_timer_init_hw()
223 cy_rslt_t result = _cyhal_timer_init_hw(obj, cfg->config, cfg->clock); in cyhal_timer_init_cfg()
311 …if(CY_RSLT_SUCCESS == _cyhal_utils_peri_pclk_set_divider(clk_dst, &obj->tcpwm.clock, (divider - 1)… in cyhal_timer_set_frequency()
313 if((CY_RSLT_SUCCESS == cyhal_clock_set_enabled(&obj->tcpwm.clock, false, false)) && in cyhal_timer_set_frequency()
314 (CY_RSLT_SUCCESS == cyhal_clock_set_frequency(&obj->tcpwm.clock, hz, &tolerance)) && in cyhal_timer_set_frequency()
315 (CY_RSLT_SUCCESS == cyhal_clock_set_enabled(&obj->tcpwm.clock, true, false))) in cyhal_timer_set_frequency()
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Dcyhal_spi.c229 …tils_peri_pclk_disable_divider(_cyhal_scb_get_clock_index(obj->resource.block_num), &(obj->clock)); in _cyhal_spi_int_frequency()
230 …pclk_set_freq(_cyhal_scb_get_clock_index(obj->resource.block_num), &(obj->clock), hz, last_ovrsmpl… in _cyhal_spi_int_frequency()
233 …utils_peri_pclk_enable_divider(_cyhal_scb_get_clock_index(obj->resource.block_num), &(obj->clock)); in _cyhal_spi_int_frequency()
237 result = cyhal_clock_set_enabled(&(obj->clock), false, false); in _cyhal_spi_int_frequency()
240 result = cyhal_clock_set_divider(&(obj->clock), last_dvdr_val); in _cyhal_spi_int_frequency()
244 result = cyhal_clock_set_enabled(&(obj->clock), true, false); in _cyhal_spi_int_frequency()
767 …result = _cyhal_utils_allocate_clock(&(obj->clock), &(obj->resource), CYHAL_CLOCK_BLOCK_PERIPHERAL… in _cyhal_spi_setup_resources()
773 obj->clock = *clk; in _cyhal_spi_setup_resources()
841 …result = _cyhal_utils_allocate_clock(&(obj->clock), &(obj->resource), CYHAL_CLOCK_BLOCK_PERIPHERAL… in _cyhal_spi_setup_resources()
846 obj->clock = *clk; in _cyhal_spi_setup_resources()
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Dcyhal_adc_mic.c288 if (NULL != cfg->clock) in _cyhal_adc_config_hw()
290 obj->clock = *cfg->clock; in _cyhal_adc_config_hw()
294 …(result = _cyhal_utils_allocate_clock(&(obj->clock), &(obj->resource), CYHAL_CLOCK_BLOCK_PERIPHERA… in _cyhal_adc_config_hw()
297 …result = cyhal_clock_set_enabled(&(obj->clock), true /* enabled */, false /* don't wait for lock. … in _cyhal_adc_config_hw()
301 if (CY_RSLT_SUCCESS == result && obj->clock.block != CYHAL_CLOCK_BLOCK_HF) in _cyhal_adc_config_hw()
303 if (CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_assign_divider(pclk, &(obj->clock))) in _cyhal_adc_config_hw()
311 …if(CY_RSLT_SUCCESS != _cyhal_utils_set_clock_frequency(&(obj->clock), _CYHAL_ADCMIC_TARGET_CLOCK_H… in _cyhal_adc_config_hw()
354 config.clock = clk; in cyhal_adc_init()
406 …cyhal_utils_peri_pclk_disable_divider(_cyhal_adcmic_clock[obj->resource.block_num], &(obj->clock)); in cyhal_adc_free()
407 cyhal_clock_free(&obj->clock); in cyhal_adc_free()
Dcyhal_pwm.c201 result = _cyhal_utils_peri_pclk_set_divider(pclk, &(obj->tcpwm.clock), div - 1); in _cyhal_pwm_update_clock_freq()
204 obj->tcpwm.clock_hz = cyhal_clock_get_frequency(&obj->tcpwm.clock); in _cyhal_pwm_update_clock_freq()
216 obj->tcpwm.clock = *clk; in _cyhal_pwm_init_clock()
217 if (CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_assign_divider(pclk, &(obj->tcpwm.clock))) in _cyhal_pwm_init_clock()
222 …else if (CY_RSLT_SUCCESS == (result = _cyhal_utils_allocate_clock(&obj->tcpwm.clock, &obj->tcpwm.r… in _cyhal_pwm_init_clock()
255 … CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_set_divider(pclk, &(obj->tcpwm.clock), div - 1) || in _cyhal_pwm_init_clock()
256 CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_enable_divider(pclk, &(obj->tcpwm.clock)) || in _cyhal_pwm_init_clock()
257 CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_assign_divider(pclk, &(obj->tcpwm.clock))) in _cyhal_pwm_init_clock()
264 obj->tcpwm.clock_hz = cyhal_clock_get_frequency(&obj->tcpwm.clock); in _cyhal_pwm_init_clock()
304 cy_rslt_t result = _cyhal_pwm_init_clock(obj, 0u, cfg->clock); in cyhal_pwm_init_cfg()
Dcyhal_quaddec.c95 …rslt = _cyhal_utils_allocate_clock(&tcpwm->clock, &tcpwm->resource, CYHAL_CLOCK_BLOCK_PERIPHERAL_1… in _cyhal_quaddec_configure_clock()
97 rslt = cyhal_clock_allocate(&tcpwm->clock, CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT); in _cyhal_quaddec_configure_clock()
117 … if (_cyhal_utils_peri_pclk_set_divider(clk_dst, &tcpwm->clock, (divider - 1)) == CY_RSLT_SUCCESS) in _cyhal_quaddec_configure_clock()
123 if (cyhal_clock_set_frequency(&tcpwm->clock, frequency, &tolerance) == CY_RSLT_SUCCESS) in _cyhal_quaddec_configure_clock()
125 … if (_cyhal_utils_peri_pclk_assign_divider(pclk, &(tcpwm->clock)) == CY_SYSCLK_SUCCESS) in _cyhal_quaddec_configure_clock()
127 cyhal_clock_set_enabled(&tcpwm->clock, true, false); in _cyhal_quaddec_configure_clock()
307 obj->tcpwm.clock = *clk; in _cyhal_quaddec_init_hw()
309 … if (_cyhal_utils_peri_pclk_assign_divider(pclk, &(obj->tcpwm.clock)) != CY_SYSCLK_SUCCESS) in _cyhal_quaddec_init_hw()
322 obj->tcpwm.clock_hz = cyhal_clock_get_frequency(&obj->tcpwm.clock); in _cyhal_quaddec_init_hw()
463 …cy_rslt_t result = _cyhal_quaddec_init_hw(obj, cfg->config, cfg->clock, 0u /* Ignored because conf… in cyhal_quaddec_init_cfg()
Dcyhal_sdhc.c912 …ret = _cyhal_utils_find_hf_source_n_divider(&(sdxx->clock), *frequency, NULL, _cyhal_sdxx_find_bes… in _cyhal_sdxx_sdcardchangeclock()
917 …ret = _cyhal_sdxx_find_best_div(cyhal_clock_get_frequency(&(sdxx->clock)), *frequency, NULL, false… in _cyhal_sdxx_sdcardchangeclock()
923 …hf_freq = cyhal_clock_get_frequency(sdxx->clock_owned ? &most_suitable_hf_source : &(sdxx->clock)); in _cyhal_sdxx_sdcardchangeclock()
934 ret = cyhal_clock_set_source(&(sdxx->clock), &most_suitable_hf_source); in _cyhal_sdxx_sdcardchangeclock()
940 ret = cyhal_clock_set_divider(&(sdxx->clock), 1); in _cyhal_sdxx_sdcardchangeclock()
1483 if (cfg->clock == NULL) in _cyhal_sdhc_init_common_hw()
1485 …result = _cyhal_utils_allocate_clock(&(sdxx->clock), &rsc, CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT, true… in _cyhal_sdhc_init_common_hw()
1490 …result = _cyhal_utils_set_clock_frequency2(&(sdxx->clock), MAX_FREQUENCY, &CYHAL_CLOCK_TOLERANCE_5… in _cyhal_sdhc_init_common_hw()
1493 if (CY_RSLT_SUCCESS == result && !cyhal_clock_is_enabled(&(sdxx->clock))) in _cyhal_sdhc_init_common_hw()
1495 result = cyhal_clock_set_enabled(&(sdxx->clock), true, true); in _cyhal_sdhc_init_common_hw()
[all …]
Dcyhal_ezi2c.c212 …result = _cyhal_utils_allocate_clock(&(obj->clock), &i2c_rsc, CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT, … in _cyhal_ezi2c_setup_resources()
217 obj->clock = *clk; in _cyhal_ezi2c_setup_resources()
358 cyhal_clock_free(&(obj->clock)); in cyhal_ezi2c_free()
400 obj->clock = *cfg->clock; in cyhal_ezi2c_init_cfg()
Dcyhal_pdmpcm.c808 uint32_t hf1_freq = cyhal_clock_get_frequency(&obj->clock); in _cyhal_pdm_pcm_set_pdl_config_struct()
922 …cy_rslt_t freq_result = _cyhal_utils_set_clock_frequency(&(obj->clock), desired_source_freq, &CLK_… in _cyhal_pdm_pcm_set_pdl_config_struct()
932 uint32_t actual_source_freq = cyhal_clock_get_frequency(&obj->clock); in _cyhal_pdm_pcm_set_pdl_config_struct()
1033 obj->clock = existing_obj->clock; in _cyhal_pdm_pcm_init_clock()
1038 if((clk_source->block != existing_obj->clock.block) || in _cyhal_pdm_pcm_init_clock()
1039 (clk_source->channel != existing_obj->clock.channel)) in _cyhal_pdm_pcm_init_clock()
1048 obj->clock = *clk_source; in _cyhal_pdm_pcm_init_clock()
1055 …result = _cyhal_utils_allocate_clock(&(obj->clock), &(obj->resource), CYHAL_CLOCK_BLOCK_PERIPHERAL… in _cyhal_pdm_pcm_init_clock()
1059 result = cyhal_clock_set_enabled(&(obj->clock), true, true); in _cyhal_pdm_pcm_init_clock()
1065 …if (CY_RSLT_SUCCESS == result && obj->clock.block != CYHAL_CLOCK_BLOCK_HF && false == obj->owned_b… in _cyhal_pdm_pcm_init_clock()
[all …]
Dcyhal_qspi.c912 if (NULL != cfg->clock) in _cyhal_qspi_init_common()
915 if (cfg->clock->block == CYHAL_CLOCK_BLOCK_HF) in _cyhal_qspi_init_common()
917 obj->clock = *cfg->clock; in _cyhal_qspi_init_common()
932 …result = _cyhal_utils_allocate_clock(&(obj->clock), &(obj->resource), CYHAL_CLOCK_BLOCK_PERIPHERAL… in _cyhal_qspi_init_common()
946 result = cyhal_clock_set_enabled(&(obj->clock), true, true); in _cyhal_qspi_init_common()
1045 .clock = clk, in cyhal_qspi_init()
1106 cyhal_clock_free(&(obj->clock)); in cyhal_qspi_free()
1125 return _cyhal_utils_set_clock_frequency2(&(obj->clock), hz, &tolerance); in cyhal_qspi_set_frequency()
1139 uint32_t freq = cyhal_clock_get_frequency(&(obj->clock)); in cyhal_qspi_get_frequency()
Dcyhal_uart.c742 …result = _cyhal_utils_allocate_clock(&(obj->clock), &obj->resource, CYHAL_CLOCK_BLOCK_PERIPHERAL_1… in _cyhal_uart_setup_resources()
748 obj->clock = *clk; in _cyhal_uart_setup_resources()
755 _cyhal_scb_get_clock_index(obj->resource.block_num), &(obj->clock)); in _cyhal_uart_setup_resources()
775 Cy_SCB_EnableClock(obj->base, cyhal_clock_get_frequency(&(obj->clock)), false); in _cyhal_uart_init_hw()
870 obj->clock = *cfg->clock; in cyhal_uart_init_cfg()
935 cyhal_clock_free(&(obj->clock)); in cyhal_uart_free()
971 status = cyhal_clock_set_enabled(&(obj->clock), false, false); in cyhal_uart_set_baud()
992 status = _cyhal_utils_peri_pclk_set_freq(0, &(obj->clock), baudrate, oversample_value); in cyhal_uart_set_baud()
994 status = cyhal_clock_set_divider(&(obj->clock), divider); in cyhal_uart_set_baud()
998 cyhal_clock_set_enabled(&(obj->clock), true, false); in cyhal_uart_set_baud()
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Dcyhal_adc_sar.c1119 obj->clock.reserved = false; in _cyhal_adc_config_hw()
1161 if (NULL != cfg->clock) in _cyhal_adc_config_hw()
1163 obj->clock = *cfg->clock; in _cyhal_adc_config_hw()
1167 …(result = _cyhal_utils_allocate_clock(&(obj->clock), &(obj->resource), CYHAL_CLOCK_BLOCK_PERIPHERA… in _cyhal_adc_config_hw()
1175 if (CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_assign_divider(pclk, &(obj->clock))) in _cyhal_adc_config_hw()
1186 … (CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_set_divider(pclk, &(obj->clock), div - 1)) || in _cyhal_adc_config_hw()
1187 (CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_enable_divider(pclk, &(obj->clock)))) in _cyhal_adc_config_hw()
1304 config.clock = clk; in cyhal_adc_init()
1366 … _cyhal_utils_peri_pclk_disable_divider(_cyhal_adc_clock[obj->resource.block_num], &(obj->clock)); in cyhal_adc_free()
1367 cyhal_clock_free(&obj->clock); in cyhal_adc_free()
[all …]
/hal_infineon-latest/mtb-hal-cat1/include_pvt/
Dcyhal_utils_impl.h176 cy_rslt_t _cyhal_utils_allocate_clock(cyhal_clock_t *clock, const cyhal_resource_inst_t *clocked_it…
189 cy_rslt_t _cyhal_utils_set_clock_frequency(cyhal_clock_t* clock, uint32_t hz, const cyhal_clock_tol…
225 cy_rslt_t _cyhal_utils_find_hf_source_n_divider(cyhal_clock_t *clock, uint32_t hz,
240 cy_rslt_t _cyhal_utils_set_clock_frequency2(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_to…
253 …_cyhal_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest, const cyhal_clock_t *clock, uint32_t div) in _cyhal_utils_peri_pclk_set_divider() argument
256 …PclkSetDivider(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel, d… in _cyhal_utils_peri_pclk_set_divider()
259 …return Cy_SysClk_PeriphSetDivider(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->c… in _cyhal_utils_peri_pclk_set_divider()
262 …line uint32_t _cyhal_utils_peri_pclk_get_divider(en_clk_dst_t clk_dest, const cyhal_clock_t *clock) in _cyhal_utils_peri_pclk_get_divider() argument
265 …riPclkGetDivider(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_get_divider()
268 …return Cy_SysClk_PeriphGetDivider(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->c… in _cyhal_utils_peri_pclk_get_divider()
[all …]
Dcyhal_hw_types.h194 cyhal_clock_t clock; member
386 cyhal_clock_t clock; member
425 const cyhal_clock_t * clock; member
478 cyhal_clock_t clock; member
528 const cyhal_clock_t * clock; member
743 cyhal_clock_t clock; member
774 const cyhal_clock_t* clock; member
793 cyhal_clock_t clock; member
817 const cyhal_clock_t* clock; member
875 cyhal_clock_t clock; member
[all …]
Dcyhal_clock_impl.h330 cy_rslt_t _cyhal_clock_allocate_channel(cyhal_clock_t *clock, cyhal_clock_block_t block, const void…
370 static inline cy_rslt_t _cyhal_clock_allocate(cyhal_clock_t *clock, cyhal_clock_block_t block) in _cyhal_clock_allocate() argument
372 CY_ASSERT(NULL != clock); in _cyhal_clock_allocate()
377 : _cyhal_clock_allocate_channel(clock, block, funcs); in _cyhal_clock_allocate()
379 static inline cy_rslt_t _cyhal_clock_allocate_peri(cyhal_clock_t *clock, cyhal_clock_block_t block) in _cyhal_clock_allocate_peri() argument
381 CY_ASSERT(NULL != clock); in _cyhal_clock_allocate_peri()
384 return _cyhal_clock_allocate_channel(clock, block, funcs); in _cyhal_clock_allocate_peri()
387 #define cyhal_clock_allocate(clock, block) _cyhal_clock_allocate(clock, block) argument
Dcyhal_hw_resources.h260 …#define _CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(clock) ((clock >> 2) / PERI0_PERI_PCL… argument
261 …_CYHAL_PERIPHERAL_CLOCK_GET_GROUP(clock) ((clock >> 2) - (_CYHAL_PERIPHERAL_CLO… argument
/hal_infineon-latest/mtb-hal-cat1/include/
Dcyhal_clock.h208 cy_rslt_t cyhal_clock_get(cyhal_clock_t *clock, const cyhal_resource_inst_t *resource);
221 cy_rslt_t cyhal_clock_reserve(cyhal_clock_t *clock, const cyhal_clock_t *clock_);
237 cy_rslt_t cyhal_clock_allocate(cyhal_clock_t *clock, cyhal_clock_block_t block);
245 cyhal_clock_feature_t cyhal_clock_get_features(const cyhal_clock_t *clock);
257 bool cyhal_clock_is_enabled(const cyhal_clock_t *clock);
278 cy_rslt_t cyhal_clock_set_enabled(cyhal_clock_t *clock, bool enabled, bool wait_for_lock);
285 uint32_t cyhal_clock_get_frequency(const cyhal_clock_t *clock);
305 cy_rslt_t cyhal_clock_set_frequency(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_…
318 cy_rslt_t cyhal_clock_set_divider(cyhal_clock_t *clock, uint32_t divider);
329 cy_rslt_t cyhal_clock_get_sources(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources…
[all …]
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_sysanalog.c35 #define IS_TMR_CLK_VALID(clock) (((clock) == CY_SYSANALOG_TIMER_CLK_PERI) || \ argument
36 ((clock) == CY_SYSANALOG_TIMER_CLK_DEEPSLEEP) || \
37 ((clock) == CY_SYSANALOG_TIMER_CLK_LF))
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_sar.h862 #define CY_SAR_IS_CLK_VALID(clock) (((clock) == CY_SAR_CLK_PERI) || \ argument
863 ((clock) == CY_SAR_CLK_DEEPSLEEP))
1484 …cy_en_sar_clock_source_t clock; /**< Clock source selection (enable/disable SA… member
1682 __STATIC_INLINE void Cy_SAR_SelectClock(const SAR_Type * base, cy_en_sar_clock_source_t clock);
2450 __STATIC_INLINE void Cy_SAR_SelectClock(const SAR_Type * base, cy_en_sar_clock_source_t clock) in Cy_SAR_SelectClock() argument
2456 CY_ASSERT_L3(CY_SAR_IS_CLK_VALID(clock)); in Cy_SAR_SelectClock()
2457 PASS_SAR_CLOCK_SEL(base) = _VAL2FLD(PASS_V2_SAR_CLOCK_SEL_CLOCK_SEL, clock); in Cy_SAR_SelectClock()
2458 …_SAR_DPSLP_CTRL(base) = _BOOL2FLD(PASS_V2_SAR_DPSLP_CTRL_ENABLED, (CY_SAR_CLK_DEEPSLEEP == clock)); in Cy_SAR_SelectClock()
/hal_infineon-latest/XMCLib/drivers/src/
Dxmc_ccu4.c97 #define XMC_CCU4_SLICE_CHECK_CLOCK(clock) \ argument
98 ((clock == XMC_CCU4_CLOCK_SCU) || \
99 (clock == XMC_CCU4_CLOCK_EXTERNAL_A) || \
100 (clock == XMC_CCU4_CLOCK_EXTERNAL_B) || \
101 (clock == XMC_CCU4_CLOCK_EXTERNAL_C))
337 void XMC_CCU4_SetModuleClock(XMC_CCU4_MODULE_t *const module, const XMC_CCU4_CLOCK_t clock) in XMC_CCU4_SetModuleClock() argument
342 XMC_ASSERT("XMC_CCU4_SetModuleClock:Invalid Module Clock", XMC_CCU4_SLICE_CHECK_CLOCK(clock)); in XMC_CCU4_SetModuleClock()
346 gctrl |= ((uint32_t) clock) << CCU4_GCTRL_PCIS_Pos; in XMC_CCU4_SetModuleClock()
Dxmc_ccu8.c107 #define XMC_CCU8_SLICE_CHECK_CLOCK(clock) \ argument
108 ((clock == XMC_CCU8_CLOCK_SCU) || \
109 (clock == XMC_CCU8_CLOCK_EXTERNAL_A) || \
110 (clock == XMC_CCU8_CLOCK_EXTERNAL_B) || \
111 (clock == XMC_CCU8_CLOCK_EXTERNAL_C))
325 void XMC_CCU8_SetModuleClock(XMC_CCU8_MODULE_t *const module, const XMC_CCU8_CLOCK_t clock) in XMC_CCU8_SetModuleClock() argument
330 XMC_ASSERT("XMC_CCU8_SetModuleClock:Invalid Module Clock", XMC_CCU8_SLICE_CHECK_CLOCK(clock)); in XMC_CCU8_SetModuleClock()
334 gctrl |= ((uint32_t) clock) << CCU8_GCTRL_PCIS_Pos; in XMC_CCU8_SetModuleClock()

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