Lines Matching refs:clock
176 cy_rslt_t _cyhal_utils_allocate_clock(cyhal_clock_t *clock, const cyhal_resource_inst_t *clocked_it…
189 cy_rslt_t _cyhal_utils_set_clock_frequency(cyhal_clock_t* clock, uint32_t hz, const cyhal_clock_tol…
225 cy_rslt_t _cyhal_utils_find_hf_source_n_divider(cyhal_clock_t *clock, uint32_t hz,
240 cy_rslt_t _cyhal_utils_set_clock_frequency2(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_to…
253 …_cyhal_utils_peri_pclk_set_divider(en_clk_dst_t clk_dest, const cyhal_clock_t *clock, uint32_t div) in _cyhal_utils_peri_pclk_set_divider() argument
256 …PclkSetDivider(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel, d… in _cyhal_utils_peri_pclk_set_divider()
259 …return Cy_SysClk_PeriphSetDivider(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->c… in _cyhal_utils_peri_pclk_set_divider()
262 …line uint32_t _cyhal_utils_peri_pclk_get_divider(en_clk_dst_t clk_dest, const cyhal_clock_t *clock) in _cyhal_utils_peri_pclk_get_divider() argument
265 …riPclkGetDivider(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_get_divider()
268 …return Cy_SysClk_PeriphGetDivider(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->c… in _cyhal_utils_peri_pclk_get_divider()
271 …ls_peri_pclk_set_frac_divider(en_clk_dst_t clk_dest, const cyhal_clock_t *clock, uint32_t div_int,… in _cyhal_utils_peri_pclk_set_frac_divider() argument
274 …SetFracDivider(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel, d… in _cyhal_utils_peri_pclk_set_frac_divider()
277 …Clk_PeriphSetFracDivider(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel, d… in _cyhal_utils_peri_pclk_set_frac_divider()
280 …ls_peri_pclk_get_frac_divider(en_clk_dst_t clk_dest, const cyhal_clock_t *clock, uint32_t *div_int… in _cyhal_utils_peri_pclk_get_frac_divider() argument
283 …GetFracDivider(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel, d… in _cyhal_utils_peri_pclk_get_frac_divider()
286 …Cy_SysClk_PeriphGetFracDivider(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->chan… in _cyhal_utils_peri_pclk_get_frac_divider()
289 …ne uint32_t _cyhal_utils_peri_pclk_get_frequency(en_clk_dst_t clk_dest, const cyhal_clock_t *clock) in _cyhal_utils_peri_pclk_get_frequency() argument
292 …PclkGetFrequency(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_get_frequency()
295 …_SysClk_PeriphGetFrequency(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_get_frequency()
298 … cy_rslt_t _cyhal_utils_peri_pclk_assign_divider(en_clk_dst_t clk_dest, const cyhal_clock_t *clock) in _cyhal_utils_peri_pclk_assign_divider() argument
301 …clkAssignDivider(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_assign_divider()
303 …iphAssignDivider(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_assign_divider()
314 … cy_rslt_t _cyhal_utils_peri_pclk_enable_divider(en_clk_dst_t clk_dest, const cyhal_clock_t *clock) in _cyhal_utils_peri_pclk_enable_divider() argument
317 …clkEnableDivider(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_enable_divider()
320 …SysClk_PeriphEnableDivider(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_enable_divider()
323 …cy_rslt_t _cyhal_utils_peri_pclk_disable_divider(en_clk_dst_t clk_dest, const cyhal_clock_t *clock) in _cyhal_utils_peri_pclk_disable_divider() argument
326 …lkDisableDivider(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_disable_divider()
329 …ysClk_PeriphDisableDivider(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_disable_divider()
332 …lk_enable_phase_align_divider(en_clk_dst_t clk_dest, const cyhal_clock_t *clock, const cyhal_clock… in _cyhal_utils_peri_pclk_enable_phase_align_divider() argument
335 …PhaseAlignDivider(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel, in _cyhal_utils_peri_pclk_enable_phase_align_divider()
339 …riphEnablePhaseAlignDivider(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel, in _cyhal_utils_peri_pclk_enable_phase_align_divider()
343 …e bool _cyhal_utils_peri_pclk_is_divider_enabled(en_clk_dst_t clk_dest, const cyhal_clock_t *clock) in _cyhal_utils_peri_pclk_is_divider_enabled() argument
346 …etDividerEnabled(clk_dest, _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_is_divider_enabled()
349 …Clk_PeriphDividerIsEnabled(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_is_divider_enabled()
352 …lk_PeriphGetDividerEnabled(_CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(clock->block), clock->channel); in _cyhal_utils_peri_pclk_is_divider_enabled()