Home
last modified time | relevance | path

Searched refs:SRSS_NUM_PLL200M (Results 1 – 7 of 7) sorted by relevance

/hal_infineon-latest/mtb-hal-cat1/include_pvt/
Dcyhal_clock_impl.h43 #define SRSS_NUM_PLL (SRSS_NUM_PLL200M + SRSS_NUM_PLL400M)
286 extern const cyhal_clock_t CYHAL_CLOCK_PLL200[SRSS_NUM_PLL200M];
288 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL200M[SRSS_NUM_PLL200M];
297 #if defined(COMPONENT_CAT1B) && (defined(SRSS_NUM_PLL200M) && (SRSS_NUM_PLL200M > 0))
299 extern const cyhal_clock_t CYHAL_CLOCK_PLL[SRSS_NUM_PLL200M];
301 extern const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL[SRSS_NUM_PLL200M];
348 #if defined(SRSS_NUM_PLL200M) && (SRSS_NUM_PLL200M > 0) in _cyhal_clock_get_funcs()
Dcyhal_hw_resources.h95 #define SRSS_NUM_PLL200M SRSS_NUM_PLL macro
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_clock.c364 #if (SRSS_NUM_PLL200M > 0)
365 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL200M[SRSS_NUM_PLL200M] =
368 #if (SRSS_NUM_PLL200M > 1)
371 #if (SRSS_NUM_PLL200M > 2)
374 #if (SRSS_NUM_PLL200M > 3)
377 #if (SRSS_NUM_PLL200M > 4)
380 #if (SRSS_NUM_PLL200M > 5)
383 #if (SRSS_NUM_PLL200M > 6)
386 #if (SRSS_NUM_PLL200M > 7)
389 #if (SRSS_NUM_PLL200M > 8)
[all …]
Dcyhal_hwmgr_impl_part.h190 #define CY_CHANNEL_COUNT_CLOCK (10 + 7 + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400…
836 …PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + 11, //…
837 …PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 11, //…
839 …PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 12, //…
840 …PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 13, //…
841 …PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + 14, //…
843 …PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 14, //…
844 …PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 15, //…
845 …PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 16, //…
846 …PERI_DIV_NR + SRSS_NUM_CLKPATH + SRSS_NUM_PLL200M + SRSS_NUM_PLL400M + SRSS_NUM_HFROOT + 17, //…
Dcyhal_utils_impl.c364 return SRSS_NUM_PLL200M; in _cyhal_utils_get_clock_count()
423 return SRSS_NUM_PLL200M; in _cyhal_utils_get_clock_count()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcyw20829B0_config.h2185 #define SRSS_NUM_PLL200M 0u macro
Dcyw20829_config.h2185 #define SRSS_NUM_PLL200M 0u macro