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Searched refs:PCLK_TCPWM0_CLOCKS265 (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe1m_config.h136 PCLK_TCPWM0_CLOCKS265 = 0x0067u, /* tcpwm[0].clocks[265] */ enumerator
Dtviibe2m_config.h146 PCLK_TCPWM0_CLOCKS265 = 0x0071u, /* tcpwm[0].clocks[265] */ enumerator
Dtviibe4m_config.h146 PCLK_TCPWM0_CLOCKS265 = 0x0071u, /* tcpwm[0].clocks[265] */ enumerator
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h149 PCLK_TCPWM0_CLOCKS265 = 0x016Eu, /* tcpwm[0].clocks[265] */ enumerator
Dtviic2d6m_config.h82 PCLK_TCPWM0_CLOCKS265 = 0x0031u, /* tcpwm[0].clocks[265] */ enumerator