| /hal_gigadevice-latest/gd32l23x/standard_peripheral/source/ |
| D | gd32l23x_usart.c | 175 USART_CTL1(usart_periph) &= ~USART_CTL1_STB; in usart_stop_bit_set()
176 USART_CTL1(usart_periph) |= stblen; in usart_stop_bit_set()
249 USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF); in usart_data_first_config()
250 USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf); in usart_data_first_config()
275 USART_CTL1(usart_periph) |= USART_CTL1_DINV; in usart_invert_config()
278 USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV); in usart_invert_config()
281 USART_CTL1(usart_periph) |= USART_CTL1_TINV; in usart_invert_config()
284 USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV); in usart_invert_config()
287 USART_CTL1(usart_periph) |= USART_CTL1_RINV; in usart_invert_config()
290 USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV); in usart_invert_config()
[all …]
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/ |
| D | gd32f3x0_usart.c | 167 USART_CTL1(usart_periph) &= ~USART_CTL1_STB; in usart_stop_bit_set()
168 USART_CTL1(usart_periph) |= stblen; in usart_stop_bit_set()
241 USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF); in usart_data_first_config()
242 USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf); in usart_data_first_config()
267 USART_CTL1(usart_periph) |= USART_CTL1_DINV; in usart_invert_config()
270 USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV); in usart_invert_config()
273 USART_CTL1(usart_periph) |= USART_CTL1_TINV; in usart_invert_config()
276 USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV); in usart_invert_config()
279 USART_CTL1(usart_periph) |= USART_CTL1_RINV; in usart_invert_config()
282 USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV); in usart_invert_config()
[all …]
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/source/ |
| D | gd32a50x_usart.c | 167 USART_CTL1(usart_periph) &= ~USART_CTL1_STB; in usart_stop_bit_set()
168 USART_CTL1(usart_periph) |= stblen; in usart_stop_bit_set()
241 USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF); in usart_data_first_config()
242 USART_CTL1(usart_periph) |= msbf; in usart_data_first_config()
267 USART_CTL1(usart_periph) |= USART_CTL1_DINV; in usart_invert_config()
270 USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV); in usart_invert_config()
273 USART_CTL1(usart_periph) |= USART_CTL1_TINV; in usart_invert_config()
276 USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV); in usart_invert_config()
279 USART_CTL1(usart_periph) |= USART_CTL1_RINV; in usart_invert_config()
282 USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV); in usart_invert_config()
[all …]
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| /hal_gigadevice-latest/gd32vf103/standard_peripheral/source/ |
| D | gd32vf103_usart.c | 172 USART_CTL1(usart_periph) &= ~USART_CTL1_STB; in usart_stop_bit_set()
174 USART_CTL1(usart_periph) |= stblen; in usart_stop_bit_set()
273 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); in usart_address_config()
274 USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); in usart_address_config()
323 USART_CTL1(usart_periph) |= USART_CTL1_LMEN; in usart_lin_mode_enable()
334 USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); in usart_lin_mode_disable()
349 USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); in usart_lin_break_detection_length_config()
350 USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); in usart_lin_break_detection_length_config()
394 USART_CTL1(usart_periph) |= USART_CTL1_CKEN; in usart_synchronous_clock_enable()
405 USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); in usart_synchronous_clock_disable()
[all …]
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/source/ |
| D | gd32f403_usart.c | 177 USART_CTL1(usart_periph) &= ~USART_CTL1_STB; in usart_stop_bit_set()
179 USART_CTL1(usart_periph) |= stblen; in usart_stop_bit_set()
375 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); in usart_address_config()
376 USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); in usart_address_config()
425 USART_CTL1(usart_periph) |= USART_CTL1_LMEN; in usart_lin_mode_enable()
436 USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); in usart_lin_mode_disable()
451 USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); in usart_lin_break_detection_length_config()
452 USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); in usart_lin_break_detection_length_config()
496 USART_CTL1(usart_periph) |= USART_CTL1_CKEN; in usart_synchronous_clock_enable()
507 USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); in usart_synchronous_clock_disable()
[all …]
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| /hal_gigadevice-latest/gd32e10x/standard_peripheral/source/ |
| D | gd32e10x_usart.c | 178 USART_CTL1(usart_periph) &= ~USART_CTL1_STB; in usart_stop_bit_set()
180 USART_CTL1(usart_periph) |= stblen; in usart_stop_bit_set()
382 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); in usart_address_config()
383 USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); in usart_address_config()
432 USART_CTL1(usart_periph) |= USART_CTL1_LMEN; in usart_lin_mode_enable()
443 USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); in usart_lin_mode_disable()
458 USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); in usart_lin_break_detection_length_config()
459 USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); in usart_lin_break_detection_length_config()
503 USART_CTL1(usart_periph) |= USART_CTL1_CKEN; in usart_synchronous_clock_enable()
514 USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); in usart_synchronous_clock_disable()
[all …]
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/ |
| D | gd32f4xx_usart.c | 197 USART_CTL1(usart_periph) &= ~USART_CTL1_STB; in usart_stop_bit_set()
199 USART_CTL1(usart_periph) |= stblen; in usart_stop_bit_set()
427 USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); in usart_address_config()
428 USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); in usart_address_config()
477 USART_CTL1(usart_periph) |= USART_CTL1_LMEN; in usart_lin_mode_enable()
488 USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); in usart_lin_mode_disable()
503 USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); in usart_lin_break_detection_length_config()
504 USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); in usart_lin_break_detection_length_config()
548 USART_CTL1(usart_periph) |= USART_CTL1_CKEN; in usart_synchronous_clock_enable()
559 USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); in usart_synchronous_clock_disable()
[all …]
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_usart.c | 226 USART_CTL1(usart_periph) &= ~USART_CTL1_STB; in usart_stop_bit_set()
228 USART_CTL1(usart_periph) |= (USART_CTL1_STB & stblen); in usart_stop_bit_set()
542 USART_CTL1(usart_periph) |= USART_CTL1_LMEN; in usart_lin_mode_enable()
561 USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); in usart_lin_mode_disable()
585 USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); in usart_lin_break_detection_length_config()
587 USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); in usart_lin_break_detection_length_config()
644 USART_CTL1(usart_periph) |= USART_CTL1_CKEN; in usart_synchronous_clock_enable()
663 USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); in usart_synchronous_clock_disable()
702 ctl = USART_CTL1(usart_periph); in usart_synchronous_clock_config()
708 USART_CTL1(usart_periph) = ctl; in usart_synchronous_clock_config()
[all …]
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| /hal_gigadevice-latest/gd32vf103/standard_peripheral/include/ |
| D | gd32vf103_usart.h | 54 #define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register… macro
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/include/ |
| D | gd32f403_usart.h | 54 #define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 … macro
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| /hal_gigadevice-latest/gd32e10x/standard_peripheral/include/ |
| D | gd32e10x_usart.h | 55 #define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 … macro
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/ |
| D | gd32f4xx_usart.h | 58 #define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 … macro
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/ |
| D | gd32f3x0_usart.h | 48 #define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 … macro
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_usart.h | 46 #define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control regis… macro
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| /hal_gigadevice-latest/gd32l23x/standard_peripheral/include/ |
| D | gd32l23x_usart.h | 48 #define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control regis… macro
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/include/ |
| D | gd32e50x_usart.h | 57 #define USART_CTL1(usartx) REG32((usartx) + 0x000000010U) /*!< USART control regi… macro
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