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Searched refs:TIMER_CTL1_TI0S (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_timer.h88 #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection… macro
562 #define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall…
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_timer.h98 #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection… macro
576 #define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall…
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_timer.c1297 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
1299 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_timer.h106 #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 … macro
885 #define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall…
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_timer.c1544 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
1546 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_timer.c1676 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
1678 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_timer.c1519 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
1521 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_timer.c1548 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
1550 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_timer.c1694 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
1696 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_timer.c1552 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
1554 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_timer.h84 #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection… macro
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_timer.h99 #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection… macro
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_timer.h97 #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection… macro
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_timer.h96 #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection… macro
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_timer.h94 #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection… macro
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_timer.c1888 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()
1890 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; in timer_hall_mode_config()