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Searched refs:TIMER_CHCTL1_CH3COMCTL (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_timer.h157 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control … macro
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_timer.h186 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ macro
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_timer.h175 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control … macro
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_timer.h184 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control … macro
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_timer.h183 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ macro
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_timer.h182 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ macro
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_timer.h185 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control … macro
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_timer.c607 ctl &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); in timer_channel_output_mode_config()
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_timer.h227 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 … macro
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_timer.c873 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); in timer_channel_output_mode_config()
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_timer.c1005 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); in timer_channel_output_mode_config()
/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_timer.c845 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); in timer_channel_output_mode_config()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_timer.c878 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); in timer_channel_output_mode_config()
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_timer.c1017 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); in timer_channel_output_mode_config()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_timer.c878 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); in timer_channel_output_mode_config()
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_timer.c896 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); in timer_channel_output_mode_config()