| /hal_gigadevice-latest/gd32l23x/standard_peripheral/source/ |
| D | gd32l23x_timer.c | 58 rcu_periph_reset_enable(RCU_TIMER5RST); in timer_deinit()
59 rcu_periph_reset_disable(RCU_TIMER5RST); in timer_deinit()
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/ |
| D | gd32f4xx_timer.c | 77 rcu_periph_reset_enable(RCU_TIMER5RST); in timer_deinit()
78 rcu_periph_reset_disable(RCU_TIMER5RST); in timer_deinit()
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/source/ |
| D | gd32f403_timer.c | 65 rcu_periph_reset_enable(RCU_TIMER5RST); in timer_deinit()
66 rcu_periph_reset_disable(RCU_TIMER5RST); in timer_deinit()
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| /hal_gigadevice-latest/gd32vf103/standard_peripheral/source/ |
| D | gd32vf103_timer.c | 78 rcu_periph_reset_enable(RCU_TIMER5RST); in timer_deinit()
79 rcu_periph_reset_disable(RCU_TIMER5RST); in timer_deinit()
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/source/ |
| D | gd32e50x_timer.c | 80 rcu_periph_reset_enable(RCU_TIMER5RST); in timer_deinit()
81 rcu_periph_reset_disable(RCU_TIMER5RST); in timer_deinit()
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/ |
| D | gd32f3x0_timer.c | 67 rcu_periph_reset_enable(RCU_TIMER5RST); in timer_deinit()
68 rcu_periph_reset_disable(RCU_TIMER5RST); in timer_deinit()
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| /hal_gigadevice-latest/gd32e10x/standard_peripheral/source/ |
| D | gd32e10x_timer.c | 81 rcu_periph_reset_enable(RCU_TIMER5RST); in timer_deinit()
82 rcu_periph_reset_disable(RCU_TIMER5RST); in timer_deinit()
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| /hal_gigadevice-latest/gd32vf103/standard_peripheral/include/ |
| D | gd32vf103_rcu.h | 321 RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ enumerator
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/include/ |
| D | gd32a50x_rcu.h | 353 …RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ enumerator
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| /hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/ |
| D | gd32f3x0_rcu.h | 375 RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U), /*!< TIMER5 reset */ enumerator
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| /hal_gigadevice-latest/gd32e10x/standard_peripheral/include/ |
| D | gd32e10x_rcu.h | 378 … RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ enumerator
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| /hal_gigadevice-latest/gd32f403/standard_peripheral/include/ |
| D | gd32f403_rcu.h | 382 … RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ enumerator
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| /hal_gigadevice-latest/gd32a50x/standard_peripheral/source/ |
| D | gd32a50x_timer.c | 63 rcu_periph_reset_enable(RCU_TIMER5RST); in timer_deinit()
64 rcu_periph_reset_disable(RCU_TIMER5RST); in timer_deinit()
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| /hal_gigadevice-latest/gd32l23x/standard_peripheral/include/ |
| D | gd32l23x_rcu.h | 368 RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 reset */ enumerator
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| /hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/ |
| D | gd32f4xx_rcu.h | 687 … RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ enumerator
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| /hal_gigadevice-latest/gd32e50x/standard_peripheral/include/ |
| D | gd32e50x_rcu.h | 647 … RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ enumerator
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