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Searched refs:CFG1_PREDV (Results 1 – 3 of 3) sorted by relevance

/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_rcu.h613 #define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) macro
614 #define RCU_PREDV_DIV1 CFG1_PREDV(0) /*!< PREDV input clock…
615 #define RCU_PREDV_DIV2 CFG1_PREDV(1) /*!< PREDV input clock…
616 #define RCU_PREDV_DIV3 CFG1_PREDV(2) /*!< PREDV input clock…
617 #define RCU_PREDV_DIV4 CFG1_PREDV(3) /*!< PREDV input clock…
618 #define RCU_PREDV_DIV5 CFG1_PREDV(4) /*!< PREDV input clock…
619 #define RCU_PREDV_DIV6 CFG1_PREDV(5) /*!< PREDV input clock…
620 #define RCU_PREDV_DIV7 CFG1_PREDV(6) /*!< PREDV input clock…
621 #define RCU_PREDV_DIV8 CFG1_PREDV(7) /*!< PREDV input clock…
622 #define RCU_PREDV_DIV9 CFG1_PREDV(8) /*!< PREDV input clock…
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/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_rcu.h656 #define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) macro
657 #define RCU_PLL_PREDV1 CFG1_PREDV(0) /*!< PLL not divided */
658 #define RCU_PLL_PREDV2 CFG1_PREDV(1) /*!< PLL divided by 2 */
659 #define RCU_PLL_PREDV3 CFG1_PREDV(2) /*!< PLL divided by 3 */
660 #define RCU_PLL_PREDV4 CFG1_PREDV(3) /*!< PLL divided by 4 */
661 #define RCU_PLL_PREDV5 CFG1_PREDV(4) /*!< PLL divided by 5 */
662 #define RCU_PLL_PREDV6 CFG1_PREDV(5) /*!< PLL divided by 6 */
663 #define RCU_PLL_PREDV7 CFG1_PREDV(6) /*!< PLL divided by 7 */
664 #define RCU_PLL_PREDV8 CFG1_PREDV(7) /*!< PLL divided by 8 */
665 #define RCU_PLL_PREDV9 CFG1_PREDV(8) /*!< PLL divided by 9 */
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/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_rcu.h720 #define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0U)) macro
721 #define RCU_PLL_PREDV1 CFG1_PREDV(0) /*!< PLL not divided */
722 #define RCU_PLL_PREDV2 CFG1_PREDV(1) /*!< PLL divided by 2 */
723 #define RCU_PLL_PREDV3 CFG1_PREDV(2) /*!< PLL divided by 3 */
724 #define RCU_PLL_PREDV4 CFG1_PREDV(3) /*!< PLL divided by 4 */
725 #define RCU_PLL_PREDV5 CFG1_PREDV(4) /*!< PLL divided by 5 */
726 #define RCU_PLL_PREDV6 CFG1_PREDV(5) /*!< PLL divided by 6 */
727 #define RCU_PLL_PREDV7 CFG1_PREDV(6) /*!< PLL divided by 7 */
728 #define RCU_PLL_PREDV8 CFG1_PREDV(7) /*!< PLL divided by 8 */
729 #define RCU_PLL_PREDV9 CFG1_PREDV(8) /*!< PLL divided by 9 */
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