Lines Matching refs:CFG1_PREDV

720 #define CFG1_PREDV(regval)         (BITS(0,3) & ((uint32_t)(regval) << 0U))  macro
721 #define RCU_PLL_PREDV1              CFG1_PREDV(0)                       /*!< PLL not divided */
722 #define RCU_PLL_PREDV2              CFG1_PREDV(1)                       /*!< PLL divided by 2 */
723 #define RCU_PLL_PREDV3              CFG1_PREDV(2)                       /*!< PLL divided by 3 */
724 #define RCU_PLL_PREDV4              CFG1_PREDV(3)                       /*!< PLL divided by 4 */
725 #define RCU_PLL_PREDV5              CFG1_PREDV(4)                       /*!< PLL divided by 5 */
726 #define RCU_PLL_PREDV6              CFG1_PREDV(5)                       /*!< PLL divided by 6 */
727 #define RCU_PLL_PREDV7              CFG1_PREDV(6)                       /*!< PLL divided by 7 */
728 #define RCU_PLL_PREDV8              CFG1_PREDV(7)                       /*!< PLL divided by 8 */
729 #define RCU_PLL_PREDV9              CFG1_PREDV(8)                       /*!< PLL divided by 9 */
730 #define RCU_PLL_PREDV10             CFG1_PREDV(9)                       /*!< PLL divided by 10 */
731 #define RCU_PLL_PREDV11             CFG1_PREDV(10)                      /*!< PLL divided by 11 */
732 #define RCU_PLL_PREDV12             CFG1_PREDV(11)                      /*!< PLL divided by 12 */
733 #define RCU_PLL_PREDV13             CFG1_PREDV(12)                      /*!< PLL divided by 13 */
734 #define RCU_PLL_PREDV14             CFG1_PREDV(13)                      /*!< PLL divided by 14 */
735 #define RCU_PLL_PREDV15             CFG1_PREDV(14)                      /*!< PLL divided by 15 */
736 #define RCU_PLL_PREDV16             CFG1_PREDV(15)                      /*!< PLL divided by 16 */