Home
last modified time | relevance | path

Searched refs:EXMC_SNCTL (Results 1 – 10 of 10) sorted by relevance

/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_exmc.c71 EXMC_SNCTL = BANK0_SNCTL_RESET; in exmc_norsram_deinit()
141 snctl = EXMC_SNCTL; in exmc_norsram_init()
187 EXMC_SNCTL = snctl; in exmc_norsram_init()
200 EXMC_SNCTL |= (uint32_t)EXMC_SNCTL_NRBKEN; in exmc_norsram_enable()
211 EXMC_SNCTL &= ~(uint32_t)EXMC_SNCTL_NRBKEN; in exmc_norsram_disable()
229 EXMC_SNCTL &= ~EXMC_SNCTL_CPS; in exmc_norsram_page_size_config()
231 EXMC_SNCTL |= page_size; in exmc_norsram_page_size_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/
Dgd32vf103_exmc.c63 EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET; in exmc_norsram_deinit()
114 snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); in exmc_norsram_init()
139 EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; in exmc_norsram_init()
152 EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; in exmc_norsram_enable()
164 EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; in exmc_norsram_disable()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_exmc.c104 EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION0_RESET; in exmc_norsram_deinit()
106 EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION1_2_3_RESET; in exmc_norsram_deinit()
192 snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); in exmc_norsram_init()
238 EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; in exmc_norsram_init()
253 EXMC_SNCTL(exmc_norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; in exmc_norsram_enable()
266 EXMC_SNCTL(exmc_norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; in exmc_norsram_disable()
287 EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; in exmc_norsram_page_size_config()
290 EXMC_SNCTL(exmc_norsram_region) |= page_size; in exmc_norsram_page_size_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_exmc.c104 EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION0_RESET; in exmc_norsram_deinit()
106 EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION1_2_3_RESET; in exmc_norsram_deinit()
178 snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); in exmc_norsram_init()
224 EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; in exmc_norsram_init()
239 EXMC_SNCTL(exmc_norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; in exmc_norsram_enable()
252 EXMC_SNCTL(exmc_norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; in exmc_norsram_disable()
488 EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; in exmc_norsram_page_size_config()
491 EXMC_SNCTL(exmc_norsram_region) |= page_size; in exmc_norsram_page_size_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_exmc.c135 EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_RESET; in exmc_norsram_deinit()
220 snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); in exmc_norsram_init()
266 EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; in exmc_norsram_init()
281 EXMC_SNCTL(exmc_norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; in exmc_norsram_enable()
294 EXMC_SNCTL(exmc_norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; in exmc_norsram_disable()
728 EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY; in exmc_norsram_consecutive_clock_config()
730 EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY; in exmc_norsram_consecutive_clock_config()
752 EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; in exmc_norsram_page_size_config()
755 EXMC_SNCTL(exmc_norsram_region) |= page_size; in exmc_norsram_page_size_config()
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/include/
Dgd32vf103_exmc.h94 #define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/include/
Dgd32e10x_exmc.h48 #define EXMC_SNCTL REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash co… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/include/
Dgd32e50x_exmc.h225 #define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/include/
Dgd32f403_exmc.h225 #define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC… macro
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_exmc.h362 #define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) … macro