1 /*! 2 \file gd32e50x_exmc.h 3 \brief definitions for the EXMC 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2021, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32E50X_EXMC_H 38 #define GD32E50X_EXMC_H 39 40 #include "gd32e50x.h" 41 42 /* EXMC definitions */ 43 #define EXMC (EXMC_BASE) /*!< EXMC register base address */ 44 45 /* registers definitions */ 46 /* NOR/PSRAM */ 47 #define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register0 */ 48 #define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register0 */ 49 #define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register0 */ 50 51 #define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register1 */ 52 #define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register1 */ 53 #define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register1 */ 54 55 #define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register2 */ 56 #define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register2 */ 57 #define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register2 */ 58 59 #define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register3 */ 60 #define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register3 */ 61 #define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register3 */ 62 63 /* NAND/PC card */ 64 #define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register1 */ 65 #define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register1 */ 66 #define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register1 */ 67 #define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register1 */ 68 #define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register1 */ 69 70 #define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register2 */ 71 #define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register2 */ 72 #define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register2 */ 73 #define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register2 */ 74 #define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register2 */ 75 76 #define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register3 */ 77 #define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register3 */ 78 #define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register3 */ 79 #define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register3 */ 80 #define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */ 81 82 /* bits definitions */ 83 /* EXMC_SNCTLx,x=0..3 */ 84 #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ 85 #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */ 86 #define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ 87 #define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ 88 #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ 89 #define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ 90 #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ 91 #define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ 92 #define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ 93 #define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ 94 #define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ 95 #define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ 96 #define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */ 97 #define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ 98 #define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */ 99 100 /* EXMC_SNTCFGx,x=0..3 */ 101 #define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */ 102 #define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */ 103 #define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */ 104 #define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ 105 #define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ 106 #define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */ 107 #define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ 108 109 /* EXMC_SNWTCFGx,x=0..3 */ 110 #define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */ 111 #define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */ 112 #define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */ 113 #define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ 114 #define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ 115 116 /* EXMC_NPCTLx,x=1..3 */ 117 #define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ 118 #define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ 119 #define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ 120 #define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ 121 #define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ 122 #define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ 123 #define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ 124 #define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ 125 126 /* EXMC_NPINTENx,x=1..3 */ 127 #define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ 128 #define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ 129 #define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ 130 #define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ 131 #define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ 132 #define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ 133 #define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ 134 135 /* EXMC_NPCTCFGx,x=1..3 */ 136 #define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ 137 #define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ 138 #define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ 139 #define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ 140 141 /* EXMC_NPATCFGx,x=1..3 */ 142 #define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ 143 #define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ 144 #define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ 145 #define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ 146 147 /* EXMC_PIOTCFG3 */ 148 #define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ 149 #define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ 150 #define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ 151 #define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ 152 153 /* EXMC_NECCx,x=1,2 */ 154 #define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ 155 156 /* constants definitions */ 157 /* EXMC NOR/SRAM timing initialize struct */ 158 typedef struct 159 { 160 uint32_t asyn_access_mode; /*!< asynchronous access mode */ 161 uint32_t syn_data_latency; /*!< configure the data latency, synchronous access mode valid */ 162 uint32_t syn_clk_division; /*!< configure the clock divide ratio, synchronous access mode valid */ 163 uint32_t bus_latency; /*!< configure the bus latency */ 164 uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */ 165 uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */ 166 uint32_t asyn_address_setuptime; /*!< configure the data setup time, asynchronous access mode valid */ 167 }exmc_norsram_timing_parameter_struct; 168 169 /* EXMC NOR/SRAM initialize struct */ 170 typedef struct 171 { 172 uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ 173 uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ 174 uint32_t extended_mode; /*!< enable or disable the extended mode */ 175 uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ 176 uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ 177 uint32_t memory_write; /*!< enable or disable the write operation */ 178 uint32_t nwait_config; /*!< NWAIT signal configuration, only work in synchronous mode */ 179 uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ 180 uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ 181 uint32_t burst_mode; /*!< enable or disable the burst mode */ 182 uint32_t databus_width; /*!< specifies the databus width of external memory */ 183 uint32_t memory_type; /*!< specifies the type of external memory */ 184 uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ 185 exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing 186 parameters for read if the extended mode is used */ 187 exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */ 188 }exmc_norsram_parameter_struct; 189 190 /* EXMC NAND/PC card timing initialize struct */ 191 typedef struct 192 { 193 uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ 194 uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ 195 uint32_t waittime; /*!< configure the minimum wait time */ 196 uint32_t setuptime; /*!< configure the address setup time */ 197 }exmc_nand_pccard_timing_parameter_struct; 198 199 /* EXMC NAND initialize struct */ 200 typedef struct 201 { 202 uint32_t nand_bank; /*!< select the bank of NAND */ 203 uint32_t ecc_size; /*!< the page size for the ECC calculation */ 204 uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ 205 uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ 206 uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ 207 uint32_t databus_width; /*!< the NAND flash databus width */ 208 uint32_t wait_feature; /*!< enable or disable the wait feature */ 209 exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ 210 exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ 211 }exmc_nand_parameter_struct; 212 213 /* EXMC PC card initialize struct */ 214 typedef struct 215 { 216 uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ 217 uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ 218 uint32_t wait_feature; /*!< enable or disable the wait feature */ 219 exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */ 220 exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */ 221 exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */ 222 }exmc_pccard_parameter_struct; 223 224 /* EXMC_register address */ 225 #define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */ 226 #define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */ 227 #define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */ 228 229 #define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */ 230 #define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */ 231 #define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */ 232 #define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */ 233 #define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC registers, bank = 1,2 */ 234 235 /* CRAM page size */ 236 #define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) 237 #define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ 238 #define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ 239 #define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ 240 #define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ 241 #define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ 242 243 /* NOR bank memory data bus width */ 244 #define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) 245 #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */ 246 #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */ 247 248 /* NOR bank memory type */ 249 #define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 250 #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ 251 #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ 252 #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ 253 254 /* asynchronous access mode */ 255 #define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) 256 #define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ 257 #define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ 258 #define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ 259 #define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ 260 261 /* data latency for NOR flash */ 262 #define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) 263 #define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */ 264 #define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */ 265 #define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */ 266 #define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */ 267 #define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */ 268 #define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */ 269 #define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */ 270 #define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */ 271 #define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */ 272 #define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */ 273 #define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */ 274 #define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */ 275 #define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */ 276 #define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */ 277 #define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */ 278 #define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */ 279 280 /* synchronous clock divide ratio */ 281 #define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) 282 #define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ 283 #define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< frequency EXMC_CLK = HCLK/2 */ 284 #define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< frequency EXMC_CLK = HCLK/3 */ 285 #define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< frequency EXMC_CLK = HCLK/4 */ 286 #define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< frequency EXMC_CLK = HCLK/5 */ 287 #define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< frequency EXMC_CLK = HCLK/6 */ 288 #define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< frequency EXMC_CLK = HCLK/7 */ 289 #define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< frequency EXMC_CLK = HCLK/8 */ 290 #define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< frequency EXMC_CLK = HCLK/9 */ 291 #define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< frequency EXMC_CLK = HCLK/10 */ 292 #define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< frequency EXMC_CLK = HCLK/11 */ 293 #define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< frequency EXMC_CLK = HCLK/12 */ 294 #define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< frequency EXMC_CLK = HCLK/13 */ 295 #define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< frequency EXMC_CLK = HCLK/14 */ 296 #define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< frequency EXMC_CLK = HCLK/15 */ 297 #define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< frequency EXMC_CLK = HCLK/16 */ 298 299 /* ECC size */ 300 #define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) 301 #define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */ 302 #define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */ 303 #define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */ 304 #define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */ 305 #define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */ 306 #define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */ 307 308 /* ALE to RE delay */ 309 #define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) 310 #define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ 311 #define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ 312 #define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ 313 #define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ 314 #define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ 315 #define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ 316 #define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ 317 #define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ 318 #define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ 319 #define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ 320 #define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ 321 #define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ 322 #define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ 323 #define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ 324 #define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ 325 #define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ 326 327 /* CLE to RE delay */ 328 #define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) 329 #define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ 330 #define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ 331 #define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ 332 #define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ 333 #define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ 334 #define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ 335 #define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ 336 #define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ 337 #define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ 338 #define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ 339 #define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ 340 #define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ 341 #define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ 342 #define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ 343 #define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ 344 #define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ 345 346 /* NAND bank memory data bus width */ 347 #define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) 348 #define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */ 349 #define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */ 350 351 /* EXMC NOR/SRAM bank region definition */ 352 #define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ 353 #define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ 354 #define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ 355 #define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ 356 357 /* EXMC NOR/SRAM write mode */ 358 #define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ 359 #define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */ 360 361 /* EXMC NWAIT signal configuration */ 362 #define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ 363 #define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */ 364 365 /* EXMC NWAIT signal polarity configuration */ 366 #define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ 367 #define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */ 368 369 /* EXMC NAND/PC card bank definition */ 370 #define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */ 371 #define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */ 372 #define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */ 373 374 /* EXMC flag bits */ 375 #define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ 376 #define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ 377 #define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ 378 #define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ 379 380 /* EXMC interrupt flag bits */ 381 #define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and corresponding flag */ 382 #define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and corresponding flag */ 383 #define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and corresponding flag */ 384 385 /* function declarations */ 386 /* NOR/SRAM */ 387 /* deinitialize EXMC NOR/SRAM region */ 388 void exmc_norsram_deinit(uint32_t exmc_norsram_region); 389 /* initialize exmc_norsram_parameter_struct with the default values */ 390 void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); 391 /* initialize EXMC NOR/SRAM region */ 392 void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); 393 /* enable EXMC NOR/SRAM region */ 394 void exmc_norsram_enable(uint32_t exmc_norsram_region); 395 /* disable EXMC NOR/SRAM region */ 396 void exmc_norsram_disable(uint32_t exmc_norsram_region); 397 /* configure CRAM page size */ 398 void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size); 399 400 /* NAND */ 401 /* deinitialize EXMC NAND bank */ 402 void exmc_nand_deinit(uint32_t exmc_nand_bank); 403 /* initialize exmc_nand_parameter_struct with the default values */ 404 void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); 405 /* initialize EXMC NAND bank */ 406 void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); 407 /* enable EXMC NAND bank */ 408 void exmc_nand_enable(uint32_t exmc_nand_bank); 409 /* disable EXMC NAND bank */ 410 void exmc_nand_disable(uint32_t exmc_nand_bank); 411 /* enable or disable the EXMC NAND ECC function */ 412 void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); 413 /* get the EXMC ECC value */ 414 uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); 415 416 /* PC card */ 417 /* deinitialize EXMC PC card bank */ 418 void exmc_pccard_deinit(void); 419 /* initialize exmc_pccard_parameter_struct parameter with the default values */ 420 void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); 421 /* initialize EXMC PC card bank */ 422 void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); 423 /* enable EXMC PC card bank */ 424 void exmc_pccard_enable(void); 425 /* disable EXMC PC card bank */ 426 void exmc_pccard_disable(void); 427 428 /* interrupt & flag functions */ 429 /* enable EXMC interrupt */ 430 void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt); 431 /* disable EXMC interrupt */ 432 void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt); 433 /* get EXMC flag status */ 434 FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); 435 /* clear EXMC flag status */ 436 void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); 437 /* get EXMC interrupt flag */ 438 FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt); 439 /* clear EXMC interrupt flag */ 440 void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt); 441 442 #endif /* GD32E50X_EXMC_H */ 443
