1 /*! 2 \file gd32vf103_exmc.h 3 \brief definitions for the EXMC 4 5 \version 2019-06-05, V1.0.0, firmware for GD32VF103 6 \version 2020-08-04, V1.1.0, firmware for GD32VF103 7 */ 8 9 /* 10 Copyright (c) 2020, GigaDevice Semiconductor Inc. 11 12 Redistribution and use in source and binary forms, with or without modification, 13 are permitted provided that the following conditions are met: 14 15 1. Redistributions of source code must retain the above copyright notice, this 16 list of conditions and the following disclaimer. 17 2. Redistributions in binary form must reproduce the above copyright notice, 18 this list of conditions and the following disclaimer in the documentation 19 and/or other materials provided with the distribution. 20 3. Neither the name of the copyright holder nor the names of its contributors 21 may be used to endorse or promote products derived from this software without 22 specific prior written permission. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 OF SUCH DAMAGE. 34 */ 35 36 #ifndef GD32VF103_EXMC_H 37 #define GD32VF103_EXMC_H 38 39 #include "gd32vf103.h" 40 41 /* EXMC definitions */ 42 #define EXMC (EXMC_BASE) /*!< EXMC register base address */ 43 44 /* registers definitions */ 45 /* NOR/PSRAM */ 46 #define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ 47 #define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ 48 #define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ 49 50 /* bits definitions */ 51 /* NOR/PSRAM */ 52 /* EXMC_SNCTLx, x=0 */ 53 #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ 54 #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ 55 #define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ 56 #define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ 57 #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ 58 #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ 59 #define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ 60 #define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ 61 #define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ 62 63 /* EXMC_SNTCFGx, x=0 */ 64 #define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ 65 #define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ 66 #define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ 67 #define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ 68 69 /* constants definitions */ 70 /* EXMC NOR/SRAM timing initialize struct */ 71 typedef struct 72 { 73 uint32_t bus_latency; /*!< configure the bus latency */ 74 uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ 75 uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ 76 uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ 77 }exmc_norsram_timing_parameter_struct; 78 79 /* EXMC NOR/SRAM initialize struct */ 80 typedef struct 81 { 82 uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ 83 ControlStatus asyn_wait; /*!< enable or disable the asynchronous wait function */ 84 ControlStatus nwait_signal; /*!< enable or disable the NWAIT signal */ 85 ControlStatus memory_write; /*!< enable or disable the write operation */ 86 uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ 87 uint32_t databus_width; /*!< specifies the databus width of external memory */ 88 uint32_t memory_type; /*!< specifies the type of external memory */ 89 ControlStatus address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ 90 exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write */ 91 }exmc_norsram_parameter_struct; 92 93 /* EXMC register address */ 94 #define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ 95 #define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ 96 97 /* NOR bank memory data bus width */ 98 #define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) 99 #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ 100 #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ 101 102 /* NOR bank memory type */ 103 #define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 104 #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ 105 #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ 106 #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ 107 108 /* EXMC NOR/SRAM bank region definition */ 109 #define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ 110 111 /* EXMC NWAIT signal polarity configuration */ 112 #define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ 113 #define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ 114 115 /* function declarations */ 116 /* deinitialize EXMC NOR/SRAM region */ 117 void exmc_norsram_deinit(uint32_t norsram_region); 118 /* exmc_norsram_parameter_struct parameter initialize */ 119 void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); 120 /* initialize EXMC NOR/SRAM region */ 121 void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); 122 /* EXMC NOR/SRAM bank enable */ 123 void exmc_norsram_enable(uint32_t norsram_region); 124 /* EXMC NOR/SRAM bank disable */ 125 void exmc_norsram_disable(uint32_t norsram_region); 126 127 #endif /* GD32VF103_EXMC_H */ 128
