| /hal_espressif-latest/components/hal/esp32/include/hal/ |
| D | cache_ll.h | 98 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
104 mask |= CACHE_BUS_IBUS2; in cache_ll_l1_get_bus()
106 mask |= CACHE_BUS_IBUS1; in cache_ll_l1_get_bus()
107 mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0; in cache_ll_l1_get_bus()
109 mask |= CACHE_BUS_IBUS0; in cache_ll_l1_get_bus()
110 mask |= (vaddr_end >= IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
111 mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0; in cache_ll_l1_get_bus()
114 mask |= CACHE_BUS_DBUS1; in cache_ll_l1_get_bus()
117 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
122 return mask; in cache_ll_l1_get_bus()
[all …]
|
| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | cache_ll.h | 66 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
69 mask |= CACHE_BUS_IBUS1; in cache_ll_l1_get_bus()
71 mask |= CACHE_BUS_IBUS0; in cache_ll_l1_get_bus()
72 mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
74 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
75 mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_bus()
76 mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0; in cache_ll_l1_get_bus()
78 mask |= CACHE_BUS_DBUS1; in cache_ll_l1_get_bus()
79 mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0; in cache_ll_l1_get_bus()
80 mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0; in cache_ll_l1_get_bus()
[all …]
|
| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | cache_ll.h | 82 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
85 mask |= CACHE_BUS_IBUS0; //Both cores have their own IBUS0 in cache_ll_l1_get_bus()
87 mask |= CACHE_BUS_DBUS0; //Both cores have their own DBUS0 in cache_ll_l1_get_bus()
92 return mask; in cache_ll_l1_get_bus()
104 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus() argument
108 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
112 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_enable_bus()
114 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_enable_bus()
120 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0; in cache_ll_l1_enable_bus()
122 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0; in cache_ll_l1_enable_bus()
[all …]
|
| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | cache_ll.h | 69 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
73 mask |= CACHE_BUS_IBUS0; in cache_ll_l1_get_bus()
75 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
80 return mask; in cache_ll_l1_get_bus()
92 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus() argument
96 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
99 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; in cache_ll_l1_enable_bus()
103 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()
114 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_disable_bus() argument
118 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
[all …]
|
| D | dedic_gpio_cpu_ll.h | 22 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) in dedic_gpio_cpu_ll_enable_output() argument
24 RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); in dedic_gpio_cpu_ll_enable_output()
48 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) in dedic_gpio_cpu_ll_write_mask() argument
50 RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); in dedic_gpio_cpu_ll_write_mask()
51 RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); in dedic_gpio_cpu_ll_write_mask()
|
| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | cache_ll.h | 70 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
74 mask |= CACHE_BUS_IBUS0; in cache_ll_l1_get_bus()
76 mask |= CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
81 return mask; in cache_ll_l1_get_bus()
93 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus() argument
97 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
100 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0; in cache_ll_l1_enable_bus()
104 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()
115 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_disable_bus() argument
119 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
[all …]
|
| D | dedic_gpio_cpu_ll.h | 22 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) in dedic_gpio_cpu_ll_enable_output() argument
24 RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); in dedic_gpio_cpu_ll_enable_output()
47 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) in dedic_gpio_cpu_ll_write_mask() argument
49 RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); in dedic_gpio_cpu_ll_write_mask()
50 RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); in dedic_gpio_cpu_ll_write_mask()
|
| /hal_espressif-latest/components/hal/esp32h2/include/hal/ |
| D | cache_ll.h | 44 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
49 mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
54 return mask; in cache_ll_l1_get_bus()
66 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus() argument
70 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
73 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0; in cache_ll_l1_enable_bus()
77 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0; in cache_ll_l1_enable_bus()
88 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_disable_bus() argument
92 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
95 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0; in cache_ll_l1_disable_bus()
[all …]
|
| D | dedic_gpio_cpu_ll.h | 22 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) in dedic_gpio_cpu_ll_enable_output() argument
24 RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); in dedic_gpio_cpu_ll_enable_output()
47 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) in dedic_gpio_cpu_ll_write_mask() argument
49 RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); in dedic_gpio_cpu_ll_write_mask()
50 RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); in dedic_gpio_cpu_ll_write_mask()
|
| D | ana_cmpr_ll.h | 108 static inline void analog_cmpr_ll_enable_intr(analog_cmpr_dev_t *hw, uint32_t mask, bool enable) in analog_cmpr_ll_enable_intr() argument
111 hw->int_ena.val |= mask; in analog_cmpr_ll_enable_intr()
113 hw->int_ena.val &= ~mask; in analog_cmpr_ll_enable_intr()
135 static inline void analog_cmpr_ll_clear_intr(analog_cmpr_dev_t *hw, uint32_t mask) in analog_cmpr_ll_clear_intr() argument
137 hw->int_clr.val = mask; in analog_cmpr_ll_clear_intr()
|
| /hal_espressif-latest/components/hal/esp32c6/include/hal/ |
| D | cache_ll.h | 44 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
49 mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0; in cache_ll_l1_get_bus()
54 return mask; in cache_ll_l1_get_bus()
66 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus() argument
70 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
73 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0; in cache_ll_l1_enable_bus()
77 dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0; in cache_ll_l1_enable_bus()
88 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_disable_bus() argument
92 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
95 ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0; in cache_ll_l1_disable_bus()
[all …]
|
| D | dedic_gpio_cpu_ll.h | 22 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) in dedic_gpio_cpu_ll_enable_output() argument
24 RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask); in dedic_gpio_cpu_ll_enable_output()
47 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) in dedic_gpio_cpu_ll_write_mask() argument
49 RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value); in dedic_gpio_cpu_ll_write_mask()
50 RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value)); in dedic_gpio_cpu_ll_write_mask()
|
| /hal_espressif-latest/components/bt/host/bluedroid/bta/ar/ |
| D | bta_ar.c | 50 UINT8 mask = 0; in bta_ar_id() local
52 mask = BTA_AR_AV_MASK; in bta_ar_id()
54 mask = BTA_AR_AVK_MASK; in bta_ar_id()
57 return mask; in bta_ar_id()
106 UINT8 mask = 0; in bta_ar_reg_avdt() local
110 mask = BTA_AR_AV_MASK; in bta_ar_reg_avdt()
113 mask = BTA_AR_AVK_MASK; in bta_ar_reg_avdt()
121 if (mask) { in bta_ar_reg_avdt()
125 bta_ar_cb.avdt_registered |= mask; in bta_ar_reg_avdt()
140 UINT8 mask = 0; in bta_ar_dereg_avdt() local
[all …]
|
| /hal_espressif-latest/components/wpa_supplicant/src/utils/ |
| D | const_time.h | 99 static inline unsigned int const_time_select(unsigned int mask, in const_time_select() argument
103 return (mask & true_val) | (~mask & false_val); in const_time_select()
114 static inline int const_time_select_int(unsigned int mask, int true_val, in const_time_select_int() argument
117 return (int) const_time_select(mask, (unsigned int) true_val, in const_time_select_int()
129 static inline u8 const_time_select_u8(u8 mask, u8 true_val, u8 false_val) in const_time_select_u8() argument
131 return (u8) const_time_select(mask, true_val, false_val); in const_time_select_u8()
142 static inline s8 const_time_select_s8(u8 mask, s8 true_val, s8 false_val) in const_time_select_s8() argument
144 return (s8) const_time_select(mask, (unsigned int) true_val, in const_time_select_s8()
161 static inline void const_time_select_bin(u8 mask, const u8 *true_val, in const_time_select_bin() argument
168 dst[i] = const_time_select_u8(mask, true_val[i], false_val[i]); in const_time_select_bin()
[all …]
|
| /hal_espressif-latest/components/bt/esp_ble_mesh/mesh_common/include/ |
| D | mesh_atomic.h | 236 bt_mesh_atomic_val_t mask = BLE_MESH_ATOMIC_MASK(bit); in bt_mesh_atomic_test_and_clear_bit() local
239 old = bt_mesh_atomic_and(BLE_MESH_ATOMIC_ELEM(target, bit), ~mask); in bt_mesh_atomic_test_and_clear_bit()
241 return (old & mask) != 0; in bt_mesh_atomic_test_and_clear_bit()
257 bt_mesh_atomic_val_t mask = BLE_MESH_ATOMIC_MASK(bit); in bt_mesh_atomic_test_and_set_bit() local
260 old = bt_mesh_atomic_or(BLE_MESH_ATOMIC_ELEM(target, bit), mask); in bt_mesh_atomic_test_and_set_bit()
262 return (old & mask) != 0; in bt_mesh_atomic_test_and_set_bit()
278 bt_mesh_atomic_val_t mask = BLE_MESH_ATOMIC_MASK(bit); in bt_mesh_atomic_clear_bit() local
280 (void)bt_mesh_atomic_and(BLE_MESH_ATOMIC_ELEM(target, bit), ~mask); in bt_mesh_atomic_clear_bit()
296 bt_mesh_atomic_val_t mask = BLE_MESH_ATOMIC_MASK(bit); in bt_mesh_atomic_set_bit() local
298 (void)bt_mesh_atomic_or(BLE_MESH_ATOMIC_ELEM(target, bit), mask); in bt_mesh_atomic_set_bit()
[all …]
|
| /hal_espressif-latest/components/hal/ |
| D | adc_hal.c | 31 #define adc_dma_ll_rx_clear_intr(dev, chan, mask) gdma_ll_rx_clear_interrupt_status(dev, chan… argument
32 #define adc_dma_ll_rx_enable_intr(dev, chan, mask) gdma_ll_rx_enable_interrupt(dev, chan, mask… argument
33 #define adc_dma_ll_rx_disable_intr(dev, chan, mask) gdma_ll_rx_enable_interrupt(dev, chan, mask… argument
47 #define adc_dma_ll_rx_get_intr(dev, mask) spi_ll_get_intr(dev, mask) argument
48 #define adc_dma_ll_rx_clear_intr(dev, chan, mask) spi_ll_clear_intr(dev, mask) argument
49 #define adc_dma_ll_rx_enable_intr(dev, chan, mask) spi_ll_enable_intr(dev, mask) argument
50 #define adc_dma_ll_rx_disable_intr(dev, chan, mask) spi_ll_disable_intr(dev, mask) argument
62 #define adc_dma_ll_rx_get_intr(dev, mask) ({i2s_ll_get_intr_status(dev) & mask;}) argument
63 #define adc_dma_ll_rx_clear_intr(dev, chan, mask) i2s_ll_clear_intr_status(dev, mask) argument
64 #define adc_dma_ll_rx_enable_intr(dev, chan, mask) do {((i2s_dev_t *)(dev))->int_ena.val |= ma… argument
[all …]
|
| /hal_espressif-latest/components/soc/esp32c6/include/soc/ |
| D | dport_access.h | 90 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
93 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
96 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
105 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
|
| D | soc.h | 106 #define CLEAR_PERI_REG_MASK(reg, mask) do { … argument
107 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
111 #define SET_PERI_REG_MASK(reg, mask) do { … argument
112 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
116 #define GET_PERI_REG_MASK(reg, mask) ({ … argument
117 …(READ_PERI_REG(reg) & (mask)); …
131 #define GET_PERI_REG_BITS2(reg, mask,shift) ({ … argument
132 …((READ_PERI_REG(reg)>>(shift))&(mask)); …
|
| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | dport_access.h | 87 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
90 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
93 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
102 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
|
| /hal_espressif-latest/components/soc/esp32h2/include/soc/ |
| D | dport_access.h | 89 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
92 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
95 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
104 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
|
| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | dport_access.h | 90 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
93 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
96 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
105 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
|
| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | dport_access.h | 90 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
93 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
96 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
105 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
|
| D | soc.h | 112 #define CLEAR_PERI_REG_MASK(reg, mask) do { … argument
113 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
117 #define SET_PERI_REG_MASK(reg, mask) do { … argument
118 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
122 #define GET_PERI_REG_MASK(reg, mask) ({ … argument
123 …(READ_PERI_REG(reg) & (mask)); …
137 #define GET_PERI_REG_BITS2(reg, mask,shift) ({ … argument
138 …((READ_PERI_REG(reg)>>(shift))&(mask)); …
|
| /hal_espressif-latest/components/soc/esp32s2/include/soc/ |
| D | dport_access.h | 88 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
91 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
94 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
103 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
|
| /hal_espressif-latest/components/soc/esp32/include/soc/ |
| D | dport_access.h | 181 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
184 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
187 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
196 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
|
