44     cache_bus_mask_t mask = 0;  in cache_ll_l1_get_bus()  local
49         mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0;  in cache_ll_l1_get_bus()
54     return mask;  in cache_ll_l1_get_bus()
66 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)  in cache_ll_l1_enable_bus()  argument
70 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);  in cache_ll_l1_enable_bus()
73     ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0;  in cache_ll_l1_enable_bus()
77     dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0;  in cache_ll_l1_enable_bus()
88 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)  in cache_ll_l1_disable_bus()  argument
92 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);  in cache_ll_l1_disable_bus()
95     ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0;  in cache_ll_l1_disable_bus()
99     dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0;  in cache_ll_l1_disable_bus()
112 static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)  in cache_ll_l1_enable_access_error_intr()  argument
114     SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);  in cache_ll_l1_enable_access_error_intr()
123 static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)  in cache_ll_l1_clear_access_error_intr()  argument
125     SET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);  in cache_ll_l1_clear_access_error_intr()
136 static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)  in cache_ll_l1_get_access_error_intr_status()  argument
138     return GET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG, mask);  in cache_ll_l1_get_access_error_intr_status()