31 #define adc_dma_ll_rx_clear_intr(dev, chan, mask)       gdma_ll_rx_clear_interrupt_status(dev, chan…  argument
32 #define adc_dma_ll_rx_enable_intr(dev, chan, mask)      gdma_ll_rx_enable_interrupt(dev, chan, mask…  argument
33 #define adc_dma_ll_rx_disable_intr(dev, chan, mask)     gdma_ll_rx_enable_interrupt(dev, chan, mask…  argument
47 #define adc_dma_ll_rx_get_intr(dev, mask)               spi_ll_get_intr(dev, mask)  argument
48 #define adc_dma_ll_rx_clear_intr(dev, chan, mask)       spi_ll_clear_intr(dev, mask)  argument
49 #define adc_dma_ll_rx_enable_intr(dev, chan, mask)      spi_ll_enable_intr(dev, mask)  argument
50 #define adc_dma_ll_rx_disable_intr(dev, chan, mask)     spi_ll_disable_intr(dev, mask)  argument
62 #define adc_dma_ll_rx_get_intr(dev, mask)               ({i2s_ll_get_intr_status(dev) & mask;})  argument
63 #define adc_dma_ll_rx_clear_intr(dev, chan, mask)       i2s_ll_clear_intr_status(dev, mask)  argument
64 #define adc_dma_ll_rx_enable_intr(dev, chan, mask)      do {((i2s_dev_t *)(dev))->int_ena.val |= ma…  argument
65 #define adc_dma_ll_rx_disable_intr(dev, chan, mask)     do {((i2s_dev_t *)(dev))->int_ena.val &= ~m…  argument
293 bool adc_hal_check_event(adc_hal_dma_ctx_t *hal, uint32_t mask)  in adc_hal_check_event()  argument
295     return adc_dma_ll_rx_get_intr(hal->dev, mask);  in adc_hal_check_event()
342 void adc_hal_digi_clr_intr(adc_hal_dma_ctx_t *hal, uint32_t mask)  in adc_hal_digi_clr_intr()  argument
344     adc_dma_ll_rx_clear_intr(hal->dev, hal->dma_chan, mask);  in adc_hal_digi_clr_intr()
347 void adc_hal_digi_dis_intr(adc_hal_dma_ctx_t *hal, uint32_t mask)  in adc_hal_digi_dis_intr()  argument
349     adc_dma_ll_rx_disable_intr(hal->dev, hal->dma_chan, mask);  in adc_hal_digi_dis_intr()