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Searched refs:icache (Results 1 – 16 of 16) sorted by relevance

/hal_espressif-latest/zephyr/port/host_flash/
Dcache_utils.c150 static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache) in esp_enable_cache_flash_wrap() argument
153 if (icache) { in esp_enable_cache_flash_wrap()
160 if (icache) { in esp_enable_cache_flash_wrap()
169 static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache) in esp_enable_cache_spiram_wrap() argument
172 if (icache) { in esp_enable_cache_spiram_wrap()
179 if (icache) { in esp_enable_cache_spiram_wrap()
345 static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache) in esp_enable_cache_flash_wrap() argument
348 if (icache) { in esp_enable_cache_flash_wrap()
355 if (icache) { in esp_enable_cache_flash_wrap()
364 static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache) in esp_enable_cache_spiram_wrap() argument
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/hal_espressif-latest/components/hal/esp32s3/
Drtc_cntl_hal.c93 if (!retent->tagmem.icache.enable) { in rtc_cntl_hal_disable_cpu_retention()
120 if (retent->tagmem.icache.enable) { in rtc_cntl_hal_enable_tagmem_retention()
122 retent->tagmem.icache.start_point, in rtc_cntl_hal_enable_tagmem_retention()
123 retent->tagmem.icache.vld_size, in rtc_cntl_hal_enable_tagmem_retention()
124 retent->tagmem.icache.size in rtc_cntl_hal_enable_tagmem_retention()
145 if (retent->tagmem.icache.enable) { in rtc_cntl_hal_disable_tagmem_retention()
/hal_espressif-latest/components/spi_flash/
Dcache_utils.c461 static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache) in esp_enable_cache_flash_wrap() argument
464 if (icache) { in esp_enable_cache_flash_wrap()
471 if (icache) { in esp_enable_cache_flash_wrap()
480 static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache) in esp_enable_cache_spiram_wrap() argument
483 if (icache) { in esp_enable_cache_spiram_wrap()
490 if (icache) { in esp_enable_cache_spiram_wrap()
709 static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache) in esp_enable_cache_flash_wrap() argument
712 if (icache) { in esp_enable_cache_flash_wrap()
719 if (icache) { in esp_enable_cache_flash_wrap()
728 static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache) in esp_enable_cache_spiram_wrap() argument
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/hal_espressif-latest/components/esp_hw_support/
Dsleep_cpu.c101 struct cache_mode imode = { .icache = 1 }; in cache_tagmem_retention_setup()
102 struct cache_mode dmode = { .icache = 0 }; in cache_tagmem_retention_setup()
112 s_cpu_retention.retent.tagmem.icache.start_point = index; in cache_tagmem_retention_setup()
113 s_cpu_retention.retent.tagmem.icache.size = (sets * waysgrp) & 0xff; in cache_tagmem_retention_setup()
114 s_cpu_retention.retent.tagmem.icache.vld_size = s_cpu_retention.retent.tagmem.icache.size; in cache_tagmem_retention_setup()
116 … s_cpu_retention.retent.tagmem.icache.vld_size = (code_seg_size / imode.cache_line_size) * waysgrp; in cache_tagmem_retention_setup()
118 s_cpu_retention.retent.tagmem.icache.enable = (code_seg_size != 0) ? 1 : 0; in cache_tagmem_retention_setup()
119 …he_tagmem_blk_gs = s_cpu_retention.retent.tagmem.icache.vld_size ? s_cpu_retention.retent.tagmem.i… in cache_tagmem_retention_setup()
182 s_cpu_retention.retent.tagmem.icache.enable = 0; in esp_sleep_tagmem_pd_low_init()
189 s_cpu_retention.retent.tagmem.icache.enable = 0; in esp_sleep_tagmem_pd_low_init()
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/hal_espressif-latest/components/esp_rom/patches/
Desp_rom_cache_esp32s2_esp32s3.c39 static inline void Cache_Wait_Idle(int icache) in Cache_Wait_Idle() argument
41 if (icache) { in Cache_Wait_Idle()
/hal_espressif-latest/components/hal/include/hal/
Drtc_hal.h29 } icache; member
/hal_espressif-latest/components/esp_rom/include/esp32s2/rom/
Dcache.h84 uint8_t icache; /*!< the cache index, 0 for dcache, 1 for icache */ member
906 uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t high);
/hal_espressif-latest/components/esp_rom/include/esp32s3/rom/
Dcache.h120 uint8_t icache; /*!< the cache index, 0 for dcache, 1 for icache */ member
1117 uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no);
/hal_espressif-latest/components/esp_rom/include/esp32c2/rom/
Dcache.h466 uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no);
/hal_espressif-latest/components/esp_rom/include/esp32c3/rom/
Dcache.h626 uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no);
/hal_espressif-latest/tools/esptool_py/docs/en/espefuse/inc/
Dsummary_ESP32-C6.rst16 …DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enable…
70 …DIS_DOWNLOAD_ICACHE (BLOCK0) Represents whether icache is disabled or enable…
Dsummary_ESP32-C2.rst45 …DIS_DOWNLOAD_ICACHE (BLOCK0) The bit be set to disable icache in download mo…
Dsummary_ESP32-H2.rst14 …DIS_ICACHE (BLOCK0) Represents whether icache is disabled or enable…
/hal_espressif-latest/components/efuse/esp32c6/
Desp_efuse_table.csv112 DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache
114 DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Represents whether icache
/hal_espressif-latest/components/efuse/esp32c2/
Desp_efuse_table.csv64 … EFUSE_BLK0, 37, 1, [] The bit be set to disable icache in download mode
/hal_espressif-latest/components/efuse/esp32h2/
Desp_efuse_table.csv112 DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache