1 /*
2 * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 // The HAL layer for RTC CNTL (common part)
8
9 #include "hal/rtc_hal.h"
10 #include "soc/soc_caps.h"
11 #include "esp32s3/rom/lldesc.h"
12 #include "esp32s3/rom/cache.h"
13 #include "hal/dma_types.h"
14 #include "hal/assert.h"
15 #include "esp_attr.h"
16
17 #define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */
18
19 typedef struct rtc_cntl_link_buf_conf {
20 uint32_t cfg[4]; /* 4 word for dma link buffer configuration */
21 } rtc_cntl_link_buf_conf_t;
22
rtc_cntl_hal_dma_link_init(void * elem,void * buff,int size,void * next)23 void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next)
24 {
25 HAL_ASSERT(elem != NULL);
26 HAL_ASSERT(buff != NULL);
27 HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN);
28
29 lldesc_t *plink = (lldesc_t *)elem;
30
31 plink->eof = next ? 0 : 1;
32 plink->owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
33 plink->size = size >> 4; /* in unit of 16 bytes */
34 plink->length = size >> 4;
35 plink->buf = buff;
36 plink->offset = 0;
37 plink->sosf = 0;
38 STAILQ_NEXT(plink, qe) = next;
39 return (void *)plink;
40 }
41
42 #if SOC_PM_SUPPORT_CPU_PD
43
44 #define DEFAULT_RETENTION_WAIT_CYCLES (0x7f)
45 #define DEFAULT_RETENTION_CLKOFF_WAIT_CYCLES (0xf)
46 #define DEFAULT_RETENTION_DONE_WAIT_CYCLES (0x7)
47
rtc_cntl_hal_enable_cpu_retention(void * addr)48 void rtc_cntl_hal_enable_cpu_retention(void *addr)
49 {
50 rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
51
52 if (addr) {
53 if (retent->cpu_pd_mem) {
54 lldesc_t *plink = (lldesc_t *)retent->cpu_pd_mem;
55
56 /* dma link buffer configure */
57 rtc_cntl_link_buf_conf_t *pbuf = (rtc_cntl_link_buf_conf_t *)plink->buf;
58 pbuf->cfg[0] = 0;
59 pbuf->cfg[1] = 0;
60 pbuf->cfg[2] = 0;
61 pbuf->cfg[3] = 0xfffe0000;
62
63 rtc_cntl_ll_set_cpu_retention_link_addr((uint32_t)plink);
64 rtc_cntl_ll_config_cpu_retention_timing(
65 DEFAULT_RETENTION_WAIT_CYCLES,
66 DEFAULT_RETENTION_CLKOFF_WAIT_CYCLES,
67 DEFAULT_RETENTION_DONE_WAIT_CYCLES
68 );
69 rtc_cntl_ll_enable_cpu_retention_clock();
70 rtc_cntl_ll_enable_cpu_retention();
71 #if SOC_PM_SUPPORT_TAGMEM_PD
72 if (!retent->tagmem.dcache.enable) {
73 // Here we only need to care for the safety of the PSRAM data in the DCache.
74 // Since only rodata, bss, heap data may be placed in PSRAM, and these data won't be
75 // modified in the sleep process code after now, so it is safe to writeback here.
76 Cache_WriteBack_All();
77 }
78 #endif
79 }
80 }
81 }
82
rtc_cntl_hal_disable_cpu_retention(void * addr)83 void IRAM_ATTR rtc_cntl_hal_disable_cpu_retention(void *addr)
84 {
85 rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
86
87 if (addr) {
88 if (retent->cpu_pd_mem) {
89 /* I/d-cache tagmem retention has not been included or not
90 * been enabled, after the system wakes up, all the contents
91 * of i/d-cache need to be invalidated. */
92 #if SOC_PM_SUPPORT_TAGMEM_PD
93 if (!retent->tagmem.icache.enable) {
94 Cache_Invalidate_ICache_All();
95 }
96 if (!retent->tagmem.dcache.enable) {
97 Cache_Invalidate_DCache_All();
98 }
99 #else
100 Cache_Invalidate_ICache_All();
101 Cache_Invalidate_DCache_All();
102 #endif // SOC_PM_SUPPORT_TAGMEM_PD
103 rtc_cntl_ll_disable_cpu_retention();
104 }
105 }
106 }
107
108 #endif // SOC_PM_SUPPORT_CPU_PD
109
110 #if SOC_PM_SUPPORT_TAGMEM_PD
111
rtc_cntl_hal_enable_tagmem_retention(void * addr)112 void rtc_cntl_hal_enable_tagmem_retention(void *addr)
113 {
114 rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
115
116 if (addr) {
117 if (retent->tagmem.link_addr) {
118 rtc_cntl_ll_set_tagmem_retention_link_addr((uint32_t)(retent->tagmem.link_addr));
119 rtc_cntl_ll_enable_tagmem_retention();
120 if (retent->tagmem.icache.enable) {
121 rtc_cntl_ll_enable_icache_tagmem_retention(
122 retent->tagmem.icache.start_point,
123 retent->tagmem.icache.vld_size,
124 retent->tagmem.icache.size
125 );
126 }
127 if (retent->tagmem.dcache.enable) {
128 rtc_cntl_ll_enable_dcache_tagmem_retention(
129 retent->tagmem.dcache.start_point,
130 retent->tagmem.dcache.vld_size,
131 retent->tagmem.dcache.size
132 );
133 }
134 }
135 }
136 }
137
rtc_cntl_hal_disable_tagmem_retention(void * addr)138 void IRAM_ATTR rtc_cntl_hal_disable_tagmem_retention(void *addr)
139 {
140 rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
141
142 if (addr) {
143 if (retent->tagmem.link_addr) {
144 rtc_cntl_ll_disable_tagmem_retention();
145 if (retent->tagmem.icache.enable) {
146 rtc_cntl_ll_disable_icache_tagmem_retention();
147 }
148 if (retent->tagmem.dcache.enable) {
149 rtc_cntl_ll_disable_dcache_tagmem_retention();
150 }
151 }
152 }
153 }
154
155 #endif // SOC_PM_SUPPORT_TAGMEM_PD
156
