| /hal_espressif-latest/components/hal/esp32s2/include/hal/ |
| D | i2s_ll.h | 64 static inline void i2s_ll_dma_enable_owner_check(i2s_dev_t *hw, bool en) in i2s_ll_dma_enable_owner_check() argument
66 hw->lc_conf.check_owner = en; in i2s_ll_dma_enable_owner_check()
75 static inline void i2s_ll_dma_enable_auto_write_back(i2s_dev_t *hw, bool en) in i2s_ll_dma_enable_auto_write_back() argument
77 hw->lc_conf.out_auto_wrback = en; in i2s_ll_dma_enable_auto_write_back()
86 static inline void i2s_ll_dma_enable_eof_on_fifo_empty(i2s_dev_t *hw, bool en) in i2s_ll_dma_enable_eof_on_fifo_empty() argument
88 hw->lc_conf.out_eof_mode = en; in i2s_ll_dma_enable_eof_on_fifo_empty()
96 static inline void i2s_ll_enable_clock(i2s_dev_t *hw) in i2s_ll_enable_clock() argument
98 if (hw->clkm_conf.clk_en == 0) { in i2s_ll_enable_clock()
99 hw->clkm_conf.clk_sel = 2; in i2s_ll_enable_clock()
100 hw->clkm_conf.clk_en = 1; in i2s_ll_enable_clock()
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| D | uart_ll.h | 84 FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) in uart_ll_set_sclk() argument
86 hw->conf0.tick_ref_always_on = (source_clk == UART_SCLK_APB) ? 1 : 0; in uart_ll_set_sclk()
97 FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk) in uart_ll_get_sclk() argument
99 *source_clk = hw->conf0.tick_ref_always_on ? UART_SCLK_APB : UART_SCLK_REF_TICK; in uart_ll_get_sclk()
111 FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) in uart_ll_set_baudrate() argument
118 hw->clk_div.div_int = clk_div >> 4; in uart_ll_set_baudrate()
119 hw->clk_div.div_frag = clk_div & 0xf; in uart_ll_set_baudrate()
130 FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) in uart_ll_get_baudrate() argument
132 typeof(hw->clk_div) div_reg; in uart_ll_get_baudrate()
133 div_reg.val = hw->clk_div.val; in uart_ll_get_baudrate()
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| D | i2c_ll.h | 103 static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) in i2c_ll_set_bus_timing() argument
106 hw->scl_low_period.period = bus_cfg->scl_low - 1; in i2c_ll_set_bus_timing()
107 hw->scl_high_period.period = bus_cfg->scl_high; in i2c_ll_set_bus_timing()
108 hw->scl_high_period.scl_wait_high_period = bus_cfg->scl_wait_high; in i2c_ll_set_bus_timing()
110 hw->sda_hold.time = bus_cfg->sda_hold; in i2c_ll_set_bus_timing()
111 hw->sda_sample.time = bus_cfg->sda_sample; in i2c_ll_set_bus_timing()
113 hw->scl_rstart_setup.time = bus_cfg->setup; in i2c_ll_set_bus_timing()
114 hw->scl_stop_setup.time = bus_cfg->setup; in i2c_ll_set_bus_timing()
116 hw->scl_start_hold.time = bus_cfg->hold - 1; in i2c_ll_set_bus_timing()
117 hw->scl_stop_hold.time = bus_cfg->hold; in i2c_ll_set_bus_timing()
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| /hal_espressif-latest/components/hal/esp32/include/hal/ |
| D | i2s_ll.h | 67 static inline void i2s_ll_dma_enable_owner_check(i2s_dev_t *hw, bool en) in i2s_ll_dma_enable_owner_check() argument
69 hw->lc_conf.check_owner = en; in i2s_ll_dma_enable_owner_check()
78 static inline void i2s_ll_dma_enable_auto_write_back(i2s_dev_t *hw, bool en) in i2s_ll_dma_enable_auto_write_back() argument
80 hw->lc_conf.out_auto_wrback = en; in i2s_ll_dma_enable_auto_write_back()
89 static inline void i2s_ll_dma_enable_eof_on_fifo_empty(i2s_dev_t *hw, bool en) in i2s_ll_dma_enable_eof_on_fifo_empty() argument
91 hw->lc_conf.out_eof_mode = en; in i2s_ll_dma_enable_eof_on_fifo_empty()
99 static inline void i2s_ll_enable_clock(i2s_dev_t *hw) in i2s_ll_enable_clock() argument
101 if (hw->clkm_conf.clk_en == 0) { in i2s_ll_enable_clock()
102 hw->clkm_conf.clk_en = 1; in i2s_ll_enable_clock()
103 hw->conf2.val = 0; in i2s_ll_enable_clock()
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| D | uart_ll.h | 66 FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) in uart_ll_set_sclk() argument
68 hw->conf0.tick_ref_always_on = (source_clk == UART_SCLK_APB) ? 1 : 0; in uart_ll_set_sclk()
79 FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk) in uart_ll_get_sclk() argument
81 *source_clk = hw->conf0.tick_ref_always_on ? UART_SCLK_APB : UART_SCLK_REF_TICK; in uart_ll_get_sclk()
93 FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) in uart_ll_set_baudrate() argument
100 hw->clk_div.div_int = clk_div >> 4; in uart_ll_set_baudrate()
101 hw->clk_div.div_frag = clk_div & 0xf; in uart_ll_set_baudrate()
112 FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) in uart_ll_get_baudrate() argument
114 typeof(hw->clk_div) div_reg; in uart_ll_get_baudrate()
115 div_reg.val = hw->clk_div.val; in uart_ll_get_baudrate()
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| D | spi_ll.h | 66 static inline void spi_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source) in spi_ll_set_clk_source() argument
76 static inline void spi_ll_master_init(spi_dev_t *hw) in spi_ll_master_init() argument
79 hw->ctrl2.val = 0; in spi_ll_master_init()
82 hw->user.usr_miso_highpart = 0; in spi_ll_master_init()
83 hw->user.usr_mosi_highpart = 0; in spi_ll_master_init()
86 hw->slave.val &= ~SPI_LL_UNUSED_INT_MASK; in spi_ll_master_init()
94 static inline void spi_ll_slave_init(spi_dev_t *hw) in spi_ll_slave_init() argument
97 hw->clock.val = 0; in spi_ll_slave_init()
98 hw->user.val = 0; in spi_ll_slave_init()
99 hw->ctrl.val = 0; in spi_ll_slave_init()
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| /hal_espressif-latest/components/hal/esp32s3/include/hal/ |
| D | i2s_ll.h | 55 static inline void i2s_ll_enable_clock(i2s_dev_t *hw) in i2s_ll_enable_clock() argument
57 hw->tx_clkm_conf.clk_en = 1; in i2s_ll_enable_clock()
65 static inline void i2s_ll_disable_clock(i2s_dev_t *hw) in i2s_ll_disable_clock() argument
67 hw->tx_clkm_conf.clk_en = 0; in i2s_ll_disable_clock()
75 static inline void i2s_ll_tx_enable_clock(i2s_dev_t *hw) in i2s_ll_tx_enable_clock() argument
77 hw->tx_clkm_conf.tx_clk_active = 1; in i2s_ll_tx_enable_clock()
85 static inline void i2s_ll_rx_enable_clock(i2s_dev_t *hw) in i2s_ll_rx_enable_clock() argument
87 hw->rx_clkm_conf.rx_clk_active = 1; in i2s_ll_rx_enable_clock()
95 static inline void i2s_ll_tx_disable_clock(i2s_dev_t *hw) in i2s_ll_tx_disable_clock() argument
97 hw->tx_clkm_conf.tx_clk_active = 0; in i2s_ll_tx_disable_clock()
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| D | uart_ll.h | 89 static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) in uart_ll_set_reset_core() argument
91 hw->clk_conf.rst_core = core_rst_en; in uart_ll_set_reset_core()
103 FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) in uart_ll_set_sclk() argument
108 hw->clk_conf.sclk_sel = 1; in uart_ll_set_sclk()
111 hw->clk_conf.sclk_sel = 2; in uart_ll_set_sclk()
114 hw->clk_conf.sclk_sel = 3; in uart_ll_set_sclk()
127 FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) in uart_ll_get_sclk() argument
129 switch (hw->clk_conf.sclk_sel) { in uart_ll_get_sclk()
152 FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) in uart_ll_set_baudrate() argument
163 hw->clkdiv.clkdiv = clk_div >> 4; in uart_ll_set_baudrate()
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| /hal_espressif-latest/components/hal/esp32c3/include/hal/ |
| D | i2s_ll.h | 54 static inline void i2s_ll_enable_clock(i2s_dev_t *hw) in i2s_ll_enable_clock() argument
56 hw->tx_clkm_conf.clk_en = 1; in i2s_ll_enable_clock()
64 static inline void i2s_ll_disable_clock(i2s_dev_t *hw) in i2s_ll_disable_clock() argument
66 hw->tx_clkm_conf.clk_en = 0; in i2s_ll_disable_clock()
74 static inline void i2s_ll_tx_enable_clock(i2s_dev_t *hw) in i2s_ll_tx_enable_clock() argument
76 hw->tx_clkm_conf.tx_clk_active = 1; in i2s_ll_tx_enable_clock()
84 static inline void i2s_ll_rx_enable_clock(i2s_dev_t *hw) in i2s_ll_rx_enable_clock() argument
86 hw->rx_clkm_conf.rx_clk_active = 1; in i2s_ll_rx_enable_clock()
94 static inline void i2s_ll_tx_disable_clock(i2s_dev_t *hw) in i2s_ll_tx_disable_clock() argument
96 hw->tx_clkm_conf.tx_clk_active = 0; in i2s_ll_tx_disable_clock()
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| D | uart_ll.h | 87 FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) in uart_ll_set_reset_core() argument
89 hw->clk_conf.rst_core = core_rst_en; in uart_ll_set_reset_core()
99 FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) in uart_ll_sclk_enable() argument
101 hw->clk_conf.sclk_en = 1; in uart_ll_sclk_enable()
102 hw->clk_conf.rx_sclk_en = 1; in uart_ll_sclk_enable()
103 hw->clk_conf.tx_sclk_en = 1; in uart_ll_sclk_enable()
113 FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) in uart_ll_sclk_disable() argument
115 hw->clk_conf.sclk_en = 0; in uart_ll_sclk_disable()
116 hw->clk_conf.rx_sclk_en = 0; in uart_ll_sclk_disable()
117 hw->clk_conf.tx_sclk_en = 0; in uart_ll_sclk_disable()
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| D | i2c_ll.h | 117 static inline void i2c_ll_update(i2c_dev_t *hw) in i2c_ll_update() argument
119 hw->ctr.conf_upgate = 1; in i2c_ll_update()
130 static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) in i2c_ll_set_bus_timing() argument
132 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1); in i2c_ll_set_bus_timing()
138 hw->scl_low_period.period = bus_cfg->scl_low - 1; in i2c_ll_set_bus_timing()
139 hw->scl_high_period.period = bus_cfg->scl_high; in i2c_ll_set_bus_timing()
140 hw->scl_high_period.scl_wait_high_period = bus_cfg->scl_wait_high; in i2c_ll_set_bus_timing()
142 hw->sda_hold.time = bus_cfg->sda_hold - 1; in i2c_ll_set_bus_timing()
143 hw->sda_sample.time = bus_cfg->sda_sample - 1; in i2c_ll_set_bus_timing()
145 hw->scl_rstart_setup.time = bus_cfg->setup - 1; in i2c_ll_set_bus_timing()
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| /hal_espressif-latest/components/hal/esp32c6/include/hal/ |
| D | modem_syscon_ll.h | 22 static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en) in modem_syscon_ll_enable_test_clk() argument
24 hw->test_conf.clk_en = en; in modem_syscon_ll_enable_test_clk()
28 static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en) in modem_syscon_ll_enable_data_dump_mux_clock() argument
30 hw->clk_conf.clk_data_dump_mux = en; in modem_syscon_ll_enable_data_dump_mux_clock()
34 static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en) in modem_syscon_ll_enable_etm_clock() argument
36 hw->clk_conf.clk_etm_en = en; in modem_syscon_ll_enable_etm_clock()
40 static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en) in modem_syscon_ll_enable_ieee802154_apb_clock() argument
42 hw->clk_conf.clk_zb_apb_en = en; in modem_syscon_ll_enable_ieee802154_apb_clock()
46 static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en) in modem_syscon_ll_enable_ieee802154_mac_clock() argument
48 hw->clk_conf.clk_zb_mac_en = en; in modem_syscon_ll_enable_ieee802154_mac_clock()
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| D | uart_ll.h | 36 #define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val) \ argument
37 if ((hw) == &UART0) { \
43 #define UART_LL_PCR_REG_U32_GET(hw, reg_suffix, field_suffix) \ argument
44 (((hw) == &UART0) ? \
48 #define UART_LL_PCR_REG_SET(hw, reg_suffix, field_suffix, val) \ argument
49 if ((hw) == &UART0) { \
55 #define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \ argument
56 …(((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##f…
89 FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw) in uart_ll_update() argument
91 hw->reg_update.reg_update = 1; in uart_ll_update()
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| D | i2s_ll.h | 55 static inline void i2s_ll_enable_clock(i2s_dev_t *hw) in i2s_ll_enable_clock() argument
58 (void)hw; in i2s_ll_enable_clock()
66 static inline void i2s_ll_disable_clock(i2s_dev_t *hw) in i2s_ll_disable_clock() argument
69 (void)hw; in i2s_ll_disable_clock()
77 static inline void i2s_ll_tx_enable_clock(i2s_dev_t *hw) in i2s_ll_tx_enable_clock() argument
79 (void)hw; in i2s_ll_tx_enable_clock()
88 static inline void i2s_ll_rx_enable_clock(i2s_dev_t *hw) in i2s_ll_rx_enable_clock() argument
90 (void)hw; in i2s_ll_rx_enable_clock()
99 static inline void i2s_ll_tx_disable_clock(i2s_dev_t *hw) in i2s_ll_tx_disable_clock() argument
101 (void)hw; in i2s_ll_tx_disable_clock()
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| D | pmu_ll.h | 33 FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag) in pmu_ll_hp_set_dig_power() argument
35 hw->hp_sys[mode].dig_power.val = flag; in pmu_ll_hp_set_dig_power()
38 FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func) in pmu_ll_hp_set_icg_func() argument
40 hw->hp_sys[mode].icg_func = icg_func; in pmu_ll_hp_set_icg_func()
43 FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap) in pmu_ll_hp_set_icg_apb() argument
45 hw->hp_sys[mode].icg_apb = bitmap; in pmu_ll_hp_set_icg_apb()
48 FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code) in pmu_ll_hp_set_icg_modem() argument
50 hw->hp_sys[mode].icg_modem.code = code; in pmu_ll_hp_set_icg_modem()
53 FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wak… in pmu_ll_hp_set_uart_wakeup_enable() argument
55 hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en; in pmu_ll_hp_set_uart_wakeup_enable()
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| D | modem_lpcon_ll.h | 22 static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en) in modem_lpcon_ll_enable_test_clk() argument
24 hw->test_conf.clk_en = en; in modem_lpcon_ll_enable_test_clk()
28 static inline void modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(modem_lpcon_dev_t *hw, bool en) in modem_lpcon_ll_enable_ble_rtc_timer_slow_osc() argument
30 hw->lp_timer_conf.clk_lp_timer_sel_osc_slow = en; in modem_lpcon_ll_enable_ble_rtc_timer_slow_osc()
34 static inline void modem_lpcon_ll_enable_ble_rtc_timer_fast_osc(modem_lpcon_dev_t *hw, bool en) in modem_lpcon_ll_enable_ble_rtc_timer_fast_osc() argument
36 hw->lp_timer_conf.clk_lp_timer_sel_osc_fast = en; in modem_lpcon_ll_enable_ble_rtc_timer_fast_osc()
40 static inline void modem_lpcon_ll_enable_ble_rtc_timer_main_xtal(modem_lpcon_dev_t *hw, bool en) in modem_lpcon_ll_enable_ble_rtc_timer_main_xtal() argument
42 hw->lp_timer_conf.clk_lp_timer_sel_xtal = en; in modem_lpcon_ll_enable_ble_rtc_timer_main_xtal()
46 static inline void modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(modem_lpcon_dev_t *hw, bool en) in modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal() argument
48 hw->lp_timer_conf.clk_lp_timer_sel_xtal32k = en; in modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal()
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| D | i2c_ll.h | 116 static inline void i2c_ll_update(i2c_dev_t *hw) in i2c_ll_update() argument
118 hw->ctr.conf_upgate = 1; in i2c_ll_update()
129 static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) in i2c_ll_set_bus_timing() argument
141 hw->scl_low_period.scl_low_period = bus_cfg->scl_low - 1; in i2c_ll_set_bus_timing()
142 hw->scl_high_period.scl_high_period = bus_cfg->scl_high; in i2c_ll_set_bus_timing()
143 hw->scl_high_period.scl_wait_high_period = bus_cfg->scl_wait_high; in i2c_ll_set_bus_timing()
145 hw->sda_hold.sda_hold_time = bus_cfg->sda_hold - 1; in i2c_ll_set_bus_timing()
146 hw->sda_sample.sda_sample_time = bus_cfg->sda_sample - 1; in i2c_ll_set_bus_timing()
148 hw->scl_rstart_setup.scl_rstart_setup_time = bus_cfg->setup - 1; in i2c_ll_set_bus_timing()
149 hw->scl_stop_setup.scl_stop_setup_time = bus_cfg->setup - 1; in i2c_ll_set_bus_timing()
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| D | rwdt_ll.h | 21 #define rwdt_ll_enable(hw) \ argument
22 lpwdt_ll_enable(hw)
24 #define rwdt_ll_disable(hw) \ argument
25 lpwdt_ll_disable(hw)
27 #define rwdt_ll_check_if_enabled(hw) \ argument
28 lpwdt_ll_check_if_enabled(hw)
30 #define rwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) \ argument
31 lpwdt_ll_config_stage(hw, stage, timeout_ticks, behavior)
33 #define rwdt_ll_disable_stage(hw, stage) \ argument
34 lpwdt_ll_disable_stage(hw, stage)
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| /hal_espressif-latest/components/hal/esp32h2/include/hal/ |
| D | uart_ll.h | 38 #define UART_LL_PCR_REG_U32_SET(hw, reg_suffix, field_suffix, val) \ argument
39 if ((hw) == &UART0) { \
45 #define UART_LL_PCR_REG_U32_GET(hw, reg_suffix, field_suffix) \ argument
46 (((hw) == &UART0) ? \
50 #define UART_LL_PCR_REG_SET(hw, reg_suffix, field_suffix, val) \ argument
51 if ((hw) == &UART0) { \
57 #define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \ argument
58 …(((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##f…
110 FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw) in uart_ll_update() argument
112 hw->reg_update.reg_update = 1; in uart_ll_update()
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| D | modem_syscon_ll.h | 22 static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en) in modem_syscon_ll_enable_test_clk() argument
24 hw->test_conf.clk_en = en; in modem_syscon_ll_enable_test_clk()
29 static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en) in modem_syscon_ll_enable_data_dump_mux_clock() argument
35 static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en) in modem_syscon_ll_enable_etm_clock() argument
37 hw->clk_conf.clk_etm_en = en; in modem_syscon_ll_enable_etm_clock()
41 static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en) in modem_syscon_ll_enable_ieee802154_apb_clock() argument
43 hw->clk_conf.clk_zb_apb_en = en; in modem_syscon_ll_enable_ieee802154_apb_clock()
47 static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en) in modem_syscon_ll_enable_ieee802154_mac_clock() argument
49 hw->clk_conf.clk_zb_mac_en = en; in modem_syscon_ll_enable_ieee802154_mac_clock()
53 static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en) in modem_syscon_ll_enable_modem_sec_clock() argument
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| D | i2s_ll.h | 56 static inline void i2s_ll_enable_clock(i2s_dev_t *hw) in i2s_ll_enable_clock() argument
59 (void)hw; in i2s_ll_enable_clock()
67 static inline void i2s_ll_disable_clock(i2s_dev_t *hw) in i2s_ll_disable_clock() argument
70 (void)hw; in i2s_ll_disable_clock()
78 static inline void i2s_ll_tx_enable_clock(i2s_dev_t *hw) in i2s_ll_tx_enable_clock() argument
80 (void)hw; in i2s_ll_tx_enable_clock()
89 static inline void i2s_ll_rx_enable_clock(i2s_dev_t *hw) in i2s_ll_rx_enable_clock() argument
91 (void)hw; in i2s_ll_rx_enable_clock()
100 static inline void i2s_ll_tx_disable_clock(i2s_dev_t *hw) in i2s_ll_tx_disable_clock() argument
102 (void)hw; in i2s_ll_tx_disable_clock()
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| D | pmu_ll.h | 33 FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag) in pmu_ll_hp_set_dig_power() argument
35 hw->hp_sys[mode].dig_power.val = flag; in pmu_ll_hp_set_dig_power()
38 FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func) in pmu_ll_hp_set_icg_func() argument
40 hw->hp_sys[mode].icg_func = icg_func; in pmu_ll_hp_set_icg_func()
43 FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap) in pmu_ll_hp_set_icg_apb() argument
45 hw->hp_sys[mode].icg_apb = bitmap; in pmu_ll_hp_set_icg_apb()
48 FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code) in pmu_ll_hp_set_icg_modem() argument
50 hw->hp_sys[mode].icg_modem.code = code; in pmu_ll_hp_set_icg_modem()
53 FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wak… in pmu_ll_hp_set_uart_wakeup_enable() argument
55 hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en; in pmu_ll_hp_set_uart_wakeup_enable()
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| D | i2c_ll.h | 66 #define I2C_LL_GET_NUM(hw) (hw == &I2C0 ? 0 : 1) argument
116 static inline void i2c_ll_update(i2c_dev_t *hw) in i2c_ll_update() argument
118 hw->ctr.conf_upgate = 1; in i2c_ll_update()
129 static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) in i2c_ll_set_bus_timing() argument
131 …HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2c[I2C_LL_GET_NUM(hw)].i2c_sclk_conf, i2c_sclk_div_num, bus_cf… in i2c_ll_set_bus_timing()
134 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2c[I2C_LL_GET_NUM(hw)].i2c_sclk_conf, i2c_sclk_div_a, 0); in i2c_ll_set_bus_timing()
135 HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2c[I2C_LL_GET_NUM(hw)].i2c_sclk_conf, i2c_sclk_div_b, 0); in i2c_ll_set_bus_timing()
141 hw->scl_low_period.scl_low_period = bus_cfg->scl_low - 1; in i2c_ll_set_bus_timing()
142 hw->scl_high_period.scl_high_period = bus_cfg->scl_high; in i2c_ll_set_bus_timing()
143 hw->scl_high_period.scl_wait_high_period = bus_cfg->scl_wait_high; in i2c_ll_set_bus_timing()
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| /hal_espressif-latest/components/hal/esp32c2/include/hal/ |
| D | uart_ll.h | 86 FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) in uart_ll_set_reset_core() argument
88 hw->clk_conf.rst_core = core_rst_en; in uart_ll_set_reset_core()
98 FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) in uart_ll_sclk_enable() argument
100 hw->clk_conf.sclk_en = 1; in uart_ll_sclk_enable()
101 hw->clk_conf.rx_sclk_en = 1; in uart_ll_sclk_enable()
102 hw->clk_conf.tx_sclk_en = 1; in uart_ll_sclk_enable()
112 FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) in uart_ll_sclk_disable() argument
114 hw->clk_conf.sclk_en = 0; in uart_ll_sclk_disable()
115 hw->clk_conf.rx_sclk_en = 0; in uart_ll_sclk_disable()
116 hw->clk_conf.tx_sclk_en = 0; in uart_ll_sclk_disable()
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| D | i2c_ll.h | 116 static inline void i2c_ll_update(i2c_dev_t *hw) in i2c_ll_update() argument
118 hw->ctr.conf_upgate = 1; in i2c_ll_update()
129 static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg) in i2c_ll_set_bus_timing() argument
131 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1); in i2c_ll_set_bus_timing()
137 hw->scl_low_period.scl_low_period = bus_cfg->scl_low - 1; in i2c_ll_set_bus_timing()
138 hw->scl_high_period.scl_high_period = bus_cfg->scl_high; in i2c_ll_set_bus_timing()
139 hw->scl_high_period.scl_wait_high_period = bus_cfg->scl_wait_high; in i2c_ll_set_bus_timing()
141 hw->sda_hold.sda_hold_time = bus_cfg->sda_hold - 1; in i2c_ll_set_bus_timing()
142 hw->sda_sample.sda_sample_time = bus_cfg->sda_sample - 1; in i2c_ll_set_bus_timing()
144 hw->scl_rstart_setup.scl_rstart_setup_time = bus_cfg->setup - 1; in i2c_ll_set_bus_timing()
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