Lines Matching refs:hw
86 FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) in uart_ll_set_reset_core() argument
88 hw->clk_conf.rst_core = core_rst_en; in uart_ll_set_reset_core()
98 FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) in uart_ll_sclk_enable() argument
100 hw->clk_conf.sclk_en = 1; in uart_ll_sclk_enable()
101 hw->clk_conf.rx_sclk_en = 1; in uart_ll_sclk_enable()
102 hw->clk_conf.tx_sclk_en = 1; in uart_ll_sclk_enable()
112 FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) in uart_ll_sclk_disable() argument
114 hw->clk_conf.sclk_en = 0; in uart_ll_sclk_disable()
115 hw->clk_conf.rx_sclk_en = 0; in uart_ll_sclk_disable()
116 hw->clk_conf.tx_sclk_en = 0; in uart_ll_sclk_disable()
128 FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk) in uart_ll_set_sclk() argument
133 hw->clk_conf.sclk_sel = 1; in uart_ll_set_sclk()
136 hw->clk_conf.sclk_sel = 2; in uart_ll_set_sclk()
139 hw->clk_conf.sclk_sel = 3; in uart_ll_set_sclk()
152 FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk) in uart_ll_get_sclk() argument
154 switch (hw->clk_conf.sclk_sel) { in uart_ll_get_sclk()
177 FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq) in uart_ll_set_baudrate() argument
188 hw->clk_div.div_int = clk_div >> 4; in uart_ll_set_baudrate()
189 hw->clk_div.div_frag = clk_div & 0xf; in uart_ll_set_baudrate()
190 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1); in uart_ll_set_baudrate()
202 FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq) in uart_ll_get_baudrate() argument
204 typeof(hw->clk_div) div_reg; in uart_ll_get_baudrate()
205 div_reg.val = hw->clk_div.val; in uart_ll_get_baudrate()
207 …(((div_reg.div_int << 4) | div_reg.div_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_di… in uart_ll_get_baudrate()
218 FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask) in uart_ll_ena_intr_mask() argument
220 hw->int_ena.val |= mask; in uart_ll_ena_intr_mask()
231 FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask) in uart_ll_disable_intr_mask() argument
233 hw->int_ena.val &= (~mask); in uart_ll_disable_intr_mask()
243 static inline uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw) in uart_ll_get_intraw_mask() argument
245 return hw->int_raw.val; in uart_ll_get_intraw_mask()
255 FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw) in uart_ll_get_intsts_mask() argument
257 return hw->int_st.val; in uart_ll_get_intsts_mask()
268 FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask) in uart_ll_clr_intsts_mask() argument
270 hw->int_clr.val = mask; in uart_ll_clr_intsts_mask()
280 FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw) in uart_ll_get_intr_ena_status() argument
282 return hw->int_ena.val; in uart_ll_get_intr_ena_status()
294 FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len) in uart_ll_read_rxfifo() argument
297 buf[i] = hw->ahb_fifo.rw_byte; in uart_ll_read_rxfifo()
310 FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len) in uart_ll_write_txfifo() argument
313 hw->ahb_fifo.rw_byte = buf[i]; in uart_ll_write_txfifo()
324 FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw) in uart_ll_rxfifo_rst() argument
326 hw->conf0.rxfifo_rst = 1; in uart_ll_rxfifo_rst()
327 hw->conf0.rxfifo_rst = 0; in uart_ll_rxfifo_rst()
337 FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw) in uart_ll_txfifo_rst() argument
339 hw->conf0.txfifo_rst = 1; in uart_ll_txfifo_rst()
340 hw->conf0.txfifo_rst = 0; in uart_ll_txfifo_rst()
350 FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) in uart_ll_get_rxfifo_len() argument
352 return hw->status.rxfifo_cnt; in uart_ll_get_rxfifo_len()
362 FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) in uart_ll_get_txfifo_len() argument
364 return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt; in uart_ll_get_txfifo_len()
375 FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit) in uart_ll_set_stop_bits() argument
377 hw->conf0.stop_bit_num = stop_bit; in uart_ll_set_stop_bits()
388 FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit) in uart_ll_get_stop_bits() argument
390 *stop_bit = (uart_stop_bits_t)hw->conf0.stop_bit_num; in uart_ll_get_stop_bits()
401 FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode) in uart_ll_set_parity() argument
404 hw->conf0.parity = parity_mode & 0x1; in uart_ll_set_parity()
406 hw->conf0.parity_en = (parity_mode >> 1) & 0x1; in uart_ll_set_parity()
417 FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode) in uart_ll_get_parity() argument
419 if (hw->conf0.parity_en) { in uart_ll_get_parity()
420 *parity_mode = (uart_parity_t)(0x2 | hw->conf0.parity); in uart_ll_get_parity()
435 FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) in uart_ll_set_rxfifo_full_thr() argument
437 hw->conf1.rxfifo_full_thrhd = full_thrhd; in uart_ll_set_rxfifo_full_thr()
449 FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) in uart_ll_set_txfifo_empty_thr() argument
451 hw->conf1.txfifo_empty_thrhd = empty_thrhd; in uart_ll_set_txfifo_empty_thr()
463 FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr) in uart_ll_set_rx_idle_thr() argument
465 hw->idle_conf.rx_idle_thrhd = rx_idle_thr; in uart_ll_set_rx_idle_thr()
476 FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num) in uart_ll_set_tx_idle_num() argument
478 hw->idle_conf.tx_idle_num = idle_num; in uart_ll_set_tx_idle_num()
489 FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num) in uart_ll_tx_break() argument
492 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf, tx_brk_num, break_num); in uart_ll_tx_break()
493 hw->conf0.txd_brk = 1; in uart_ll_tx_break()
495 hw->conf0.txd_brk = 0; in uart_ll_tx_break()
508 FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, ui… in uart_ll_set_hw_flow_ctrl() argument
512 hw->mem_conf.rx_flow_thrhd = rx_thrs; in uart_ll_set_hw_flow_ctrl()
513 hw->conf1.rx_flow_en = 1; in uart_ll_set_hw_flow_ctrl()
515 hw->conf1.rx_flow_en = 0; in uart_ll_set_hw_flow_ctrl()
518 hw->conf0.tx_flow_en = 1; in uart_ll_set_hw_flow_ctrl()
520 hw->conf0.tx_flow_en = 0; in uart_ll_set_hw_flow_ctrl()
532 FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl) in uart_ll_get_hw_flow_ctrl() argument
535 if (hw->conf1.rx_flow_en) { in uart_ll_get_hw_flow_ctrl()
538 if (hw->conf0.tx_flow_en) { in uart_ll_get_hw_flow_ctrl()
552 FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool… in uart_ll_set_sw_flow_ctrl() argument
555 hw->flow_conf.xonoff_del = 1; in uart_ll_set_sw_flow_ctrl()
556 hw->flow_conf.sw_flow_con_en = 1; in uart_ll_set_sw_flow_ctrl()
557 hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd; in uart_ll_set_sw_flow_ctrl()
558 hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd; in uart_ll_set_sw_flow_ctrl()
559 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char); in uart_ll_set_sw_flow_ctrl()
560 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char); in uart_ll_set_sw_flow_ctrl()
562 hw->flow_conf.sw_flow_con_en = 0; in uart_ll_set_sw_flow_ctrl()
563 hw->flow_conf.xonoff_del = 0; in uart_ll_set_sw_flow_ctrl()
580 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char) in uart_ll_set_at_cmd_char() argument
582 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char); in uart_ll_set_at_cmd_char()
583 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num); in uart_ll_set_at_cmd_char()
584 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle); in uart_ll_set_at_cmd_char()
585 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle); in uart_ll_set_at_cmd_char()
586 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout); in uart_ll_set_at_cmd_char()
597 FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit) in uart_ll_set_data_bit_num() argument
599 hw->conf0.bit_num = data_bit; in uart_ll_set_data_bit_num()
610 FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level) in uart_ll_set_rts_active_level() argument
612 hw->conf0.sw_rts = level & 0x1; in uart_ll_set_rts_active_level()
623 FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level) in uart_ll_set_dtr_active_level() argument
625 hw->conf0.sw_dtr = level & 0x1; in uart_ll_set_dtr_active_level()
637 FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd) in uart_ll_set_wakeup_thrd() argument
640 hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; in uart_ll_set_wakeup_thrd()
650 FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw) in uart_ll_set_mode_normal() argument
652 hw->rs485_conf.en = 0; in uart_ll_set_mode_normal()
653 hw->rs485_conf.tx_rx_en = 0; in uart_ll_set_mode_normal()
654 hw->rs485_conf.rx_busy_tx_en = 0; in uart_ll_set_mode_normal()
655 hw->conf0.irda_en = 0; in uart_ll_set_mode_normal()
665 FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw) in uart_ll_set_mode_rs485_app_ctrl() argument
668 hw->rs485_conf.rx_busy_tx_en = 1; in uart_ll_set_mode_rs485_app_ctrl()
669 hw->conf0.irda_en = 0; in uart_ll_set_mode_rs485_app_ctrl()
670 hw->conf0.sw_rts = 0; in uart_ll_set_mode_rs485_app_ctrl()
671 hw->conf0.irda_en = 0; in uart_ll_set_mode_rs485_app_ctrl()
672 hw->rs485_conf.dl0_en = 1; in uart_ll_set_mode_rs485_app_ctrl()
673 hw->rs485_conf.dl1_en = 1; in uart_ll_set_mode_rs485_app_ctrl()
674 hw->rs485_conf.en = 1; in uart_ll_set_mode_rs485_app_ctrl()
684 FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw) in uart_ll_set_mode_rs485_half_duplex() argument
687 hw->conf0.sw_rts = 1; in uart_ll_set_mode_rs485_half_duplex()
689 hw->rs485_conf.tx_rx_en = 0; in uart_ll_set_mode_rs485_half_duplex()
692 hw->rs485_conf.rx_busy_tx_en = 0; in uart_ll_set_mode_rs485_half_duplex()
693 hw->conf0.irda_en = 0; in uart_ll_set_mode_rs485_half_duplex()
694 hw->rs485_conf.dl0_en = 1; in uart_ll_set_mode_rs485_half_duplex()
695 hw->rs485_conf.dl1_en = 1; in uart_ll_set_mode_rs485_half_duplex()
696 hw->rs485_conf.en = 1; in uart_ll_set_mode_rs485_half_duplex()
706 FORCE_INLINE_ATTR bool uart_ll_is_mode_rs485_half_duplex(uart_dev_t *hw) in uart_ll_is_mode_rs485_half_duplex() argument
708 return (!hw->rs485_conf.rx_busy_tx_en && hw->rs485_conf.en); in uart_ll_is_mode_rs485_half_duplex()
718 FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw) in uart_ll_set_mode_collision_detect() argument
720 hw->conf0.irda_en = 0; in uart_ll_set_mode_collision_detect()
722 hw->rs485_conf.tx_rx_en = 1; in uart_ll_set_mode_collision_detect()
724 hw->rs485_conf.rx_busy_tx_en = 1; in uart_ll_set_mode_collision_detect()
725 hw->rs485_conf.dl0_en = 1; in uart_ll_set_mode_collision_detect()
726 hw->rs485_conf.dl1_en = 1; in uart_ll_set_mode_collision_detect()
727 hw->conf0.sw_rts = 0; in uart_ll_set_mode_collision_detect()
728 hw->rs485_conf.en = 1; in uart_ll_set_mode_collision_detect()
738 FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw) in uart_ll_set_mode_irda() argument
740 hw->rs485_conf.en = 0; in uart_ll_set_mode_irda()
741 hw->rs485_conf.tx_rx_en = 0; in uart_ll_set_mode_irda()
742 hw->rs485_conf.rx_busy_tx_en = 0; in uart_ll_set_mode_irda()
743 hw->conf0.sw_rts = 0; in uart_ll_set_mode_irda()
744 hw->conf0.irda_en = 1; in uart_ll_set_mode_irda()
755 FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode) in uart_ll_set_mode() argument
760 uart_ll_set_mode_normal(hw); in uart_ll_set_mode()
763 uart_ll_set_mode_collision_detect(hw); in uart_ll_set_mode()
766 uart_ll_set_mode_rs485_app_ctrl(hw); in uart_ll_set_mode()
769 uart_ll_set_mode_rs485_half_duplex(hw); in uart_ll_set_mode()
772 uart_ll_set_mode_irda(hw); in uart_ll_set_mode()
786 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num) in uart_ll_get_at_cmd_char() argument
788 *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data); in uart_ll_get_at_cmd_char()
789 *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num); in uart_ll_get_at_cmd_char()
799 FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw) in uart_ll_get_wakeup_thrd() argument
801 return hw->sleep_conf.active_threshold + UART_LL_MIN_WAKEUP_THRESH; in uart_ll_get_wakeup_thrd()
812 FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit) in uart_ll_get_data_bit_num() argument
814 *data_bit = (uart_word_length_t)hw->conf0.bit_num; in uart_ll_get_data_bit_num()
824 FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) in uart_ll_is_tx_idle() argument
826 return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0)); in uart_ll_is_tx_idle()
836 FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw) in uart_ll_is_hw_rts_en() argument
838 return hw->conf1.rx_flow_en; in uart_ll_is_hw_rts_en()
848 FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw) in uart_ll_is_hw_cts_en() argument
850 return hw->conf0.tx_flow_en; in uart_ll_is_hw_cts_en()
861 FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en) in uart_ll_set_loop_back() argument
863 hw->conf0.loopback = loop_back_en; in uart_ll_set_loop_back()
866 FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on) in uart_ll_xon_force_on() argument
868 hw->flow_conf.force_xon = 1; in uart_ll_xon_force_on()
870 hw->flow_conf.force_xon = 0; in uart_ll_xon_force_on()
883 FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask) in uart_ll_inverse_signal() argument
885 typeof(hw->conf0) conf0_reg; in uart_ll_inverse_signal()
886 conf0_reg.val = hw->conf0.val; in uart_ll_inverse_signal()
895 hw->conf0.val = conf0_reg.val; in uart_ll_inverse_signal()
906 FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd) in uart_ll_set_rx_tout() argument
910 hw->mem_conf.rx_tout_thrhd = tout_val; in uart_ll_set_rx_tout()
911 hw->conf1.rx_tout_en = 1; in uart_ll_set_rx_tout()
913 hw->conf1.rx_tout_en = 0; in uart_ll_set_rx_tout()
924 FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw) in uart_ll_get_rx_tout_thr() argument
927 if(hw->conf1.rx_tout_en > 0) { in uart_ll_get_rx_tout_thr()
928 tout_thrd = hw->mem_conf.rx_tout_thrhd; in uart_ll_get_rx_tout_thr()
940 FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) in uart_ll_max_tout_thrd() argument
993 FORCE_INLINE_ATTR void uart_ll_discard_error_data(uart_dev_t *hw, bool discard) in uart_ll_discard_error_data() argument
995 hw->conf0.err_wr_mask = discard ? 1 : 0; in uart_ll_discard_error_data()