33 FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag)  in pmu_ll_hp_set_dig_power()  argument
35     hw->hp_sys[mode].dig_power.val = flag;  in pmu_ll_hp_set_dig_power()
38 FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)  in pmu_ll_hp_set_icg_func()  argument
40     hw->hp_sys[mode].icg_func = icg_func;  in pmu_ll_hp_set_icg_func()
43 FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap)  in pmu_ll_hp_set_icg_apb()  argument
45     hw->hp_sys[mode].icg_apb = bitmap;  in pmu_ll_hp_set_icg_apb()
48 FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code)  in pmu_ll_hp_set_icg_modem()  argument
50     hw->hp_sys[mode].icg_modem.code = code;  in pmu_ll_hp_set_icg_modem()
53 FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wak…  in pmu_ll_hp_set_uart_wakeup_enable()  argument
55     hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en;  in pmu_ll_hp_set_uart_wakeup_enable()
58 FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_lp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_a…  in pmu_ll_hp_set_hold_all_lp_pad()  argument
60     hw->hp_sys[mode].syscntl.lp_pad_hold_all = hold_all;  in pmu_ll_hp_set_hold_all_lp_pad()
63 FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_hp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_a…  in pmu_ll_hp_set_hold_all_hp_pad()  argument
65     hw->hp_sys[mode].syscntl.hp_pad_hold_all = hold_all;  in pmu_ll_hp_set_hold_all_hp_pad()
68 FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_pad_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_se…  in pmu_ll_hp_set_dig_pad_slp_sel()  argument
70     hw->hp_sys[mode].syscntl.dig_pad_slp_sel = slp_sel;  in pmu_ll_hp_set_dig_pad_slp_sel()
73 FORCE_INLINE_ATTR void pmu_ll_hp_set_pause_watchdog(pmu_dev_t *hw, pmu_hp_mode_t mode, bool pause_w…  in pmu_ll_hp_set_pause_watchdog()  argument
75     hw->hp_sys[mode].syscntl.dig_pause_wdt = pause_wdt;  in pmu_ll_hp_set_pause_watchdog()
78 FORCE_INLINE_ATTR void pmu_ll_hp_set_cpu_stall(pmu_dev_t *hw, pmu_hp_mode_t mode, bool cpu_stall)  in pmu_ll_hp_set_cpu_stall()  argument
80     hw->hp_sys[mode].syscntl.dig_cpu_stall = cpu_stall;  in pmu_ll_hp_set_cpu_stall()
92 FORCE_INLINE_ATTR void pmu_ll_hp_set_clk_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t xpd_flag)  in pmu_ll_hp_set_clk_power()  argument
94     hw->hp_sys[mode].clk_power.val = xpd_flag;  in pmu_ll_hp_set_clk_power()
97 FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtal)  in pmu_ll_hp_set_xtal_xpd()  argument
99     hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;  in pmu_ll_hp_set_xtal_xpd()
102 FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)  in pmu_ll_hp_set_bias_xpd()  argument
104     hw->hp_sys[mode].bias.xpd_bias = xpd_bias;  in pmu_ll_hp_set_bias_xpd()
107 FORCE_INLINE_ATTR void pmu_ll_hp_set_dbg_atten(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value)  in pmu_ll_hp_set_dbg_atten()  argument
109     hw->hp_sys[mode].bias.dbg_atten = value;  in pmu_ll_hp_set_dbg_atten()
112 FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off)  in pmu_ll_hp_set_current_power_off()  argument
114     hw->hp_sys[mode].bias.pd_cur = off;  in pmu_ll_hp_set_current_power_off()
117 FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool en)  in pmu_ll_hp_set_bias_sleep_enable()  argument
119     hw->hp_sys[mode].bias.bias_sleep = en;  in pmu_ll_hp_set_bias_sleep_enable()
122 FORCE_INLINE_ATTR void pmu_ll_hp_set_retention_param(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t pa…  in pmu_ll_hp_set_retention_param()  argument
124     hw->hp_sys[mode].backup.val = param;  in pmu_ll_hp_set_retention_param()
127 FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_enable(pmu_dev_t *hw)  in pmu_ll_hp_set_sleep_to_active_backup_enable()  argument
129     hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 1;  in pmu_ll_hp_set_sleep_to_active_backup_enable()
132 FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *hw)  in pmu_ll_hp_set_sleep_to_active_backup_disable()  argument
134     hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 0;  in pmu_ll_hp_set_sleep_to_active_backup_disable()
137 FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_enable(pmu_dev_t *hw)  in pmu_ll_hp_set_modem_to_active_backup_enable()  argument
139     hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 1;  in pmu_ll_hp_set_modem_to_active_backup_enable()
142 FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_disable(pmu_dev_t *hw)  in pmu_ll_hp_set_modem_to_active_backup_disable()  argument
144     hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 0;  in pmu_ll_hp_set_modem_to_active_backup_disable()
147 FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_enable(pmu_dev_t *hw)  in pmu_ll_hp_set_sleep_to_modem_backup_enable()  argument
149     hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 1;  in pmu_ll_hp_set_sleep_to_modem_backup_enable()
152 FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_disable(pmu_dev_t *hw)  in pmu_ll_hp_set_sleep_to_modem_backup_disable()  argument
154     hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 0;  in pmu_ll_hp_set_sleep_to_modem_backup_disable()
157 FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw)  in pmu_ll_hp_set_active_to_sleep_backup_enable()  argument
159     hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 1;  in pmu_ll_hp_set_active_to_sleep_backup_enable()
162 FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *hw)  in pmu_ll_hp_set_active_to_sleep_backup_disable()  argument
164     hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 0;  in pmu_ll_hp_set_active_to_sleep_backup_disable()
167 FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_enable(pmu_dev_t *hw)  in pmu_ll_hp_set_modem_to_sleep_backup_enable()  argument
169     hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 1;  in pmu_ll_hp_set_modem_to_sleep_backup_enable()
172 FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_disable(pmu_dev_t *hw)  in pmu_ll_hp_set_modem_to_sleep_backup_disable()  argument
174     hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 0;  in pmu_ll_hp_set_modem_to_sleep_backup_disable()
177 FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t ic…  in pmu_ll_hp_set_backup_icg_func()  argument
179     hw->hp_sys[mode].backup_clk = icg_func;  in pmu_ll_hp_set_backup_icg_func()
182 FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_nodiv(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sysclk_no…  in pmu_ll_hp_set_sysclk_nodiv()  argument
184     hw->hp_sys[mode].sysclk.dig_sysclk_nodiv = sysclk_nodiv;  in pmu_ll_hp_set_sysclk_nodiv()
187 FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool icg_…  in pmu_ll_hp_set_icg_sysclk_enable()  argument
189     hw->hp_sys[mode].sysclk.icg_sysclk_en = icg_sysclk_en;  in pmu_ll_hp_set_icg_sysclk_enable()
192 FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)  in pmu_ll_hp_set_sysclk_slp_sel()  argument
194     hw->hp_sys[mode].sysclk.sysclk_slp_sel = slp_sel;  in pmu_ll_hp_set_sysclk_slp_sel()
197 FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp…  in pmu_ll_hp_set_icg_sysclk_slp_sel()  argument
199     hw->hp_sys[mode].sysclk.icg_slp_sel = slp_sel;  in pmu_ll_hp_set_icg_sysclk_slp_sel()
202 FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_sysclk(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t sysclk_…  in pmu_ll_hp_set_dig_sysclk()  argument
204     hw->hp_sys[mode].sysclk.dig_sysclk_sel = sysclk_sel;  in pmu_ll_hp_set_dig_sysclk()
207 FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, b…  in pmu_ll_hp_set_regulator_sleep_logic_xpd()  argument
209     hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd;  in pmu_ll_hp_set_regulator_sleep_logic_xpd()
212 FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, …  in pmu_ll_hp_set_regulator_sleep_memory_xpd()  argument
214     hw->hp_sys[mode].regulator0.slp_mem_xpd = slp_xpd;  in pmu_ll_hp_set_regulator_sleep_memory_xpd()
217 FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd)  in pmu_ll_hp_set_regulator_xpd()  argument
219     hw->hp_sys[mode].regulator0.xpd = xpd;  in pmu_ll_hp_set_regulator_xpd()
222 FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode,…  in pmu_ll_hp_set_regulator_sleep_logic_dbias()  argument
224     hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias;  in pmu_ll_hp_set_regulator_sleep_logic_dbias()
227 FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode…  in pmu_ll_hp_set_regulator_sleep_memory_dbias()  argument
229     hw->hp_sys[mode].regulator0.slp_mem_dbias = slp_dbias;  in pmu_ll_hp_set_regulator_sleep_memory_dbias()
232 FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t db…  in pmu_ll_hp_set_regulator_dbias()  argument
234     hw->hp_sys[mode].regulator0.dbias = dbias;  in pmu_ll_hp_set_regulator_dbias()
237 FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32…  in pmu_ll_hp_set_regulator_driver_bar()  argument
239     hw->hp_sys[mode].regulator1.drv_b = drv_b;  in pmu_ll_hp_set_regulator_driver_bar()
243 FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_slp_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_…  in pmu_ll_lp_set_regulator_slp_xpd()  argument
245     hw->lp_sys[mode].regulator0.slp_xpd = slp_xpd;  in pmu_ll_lp_set_regulator_slp_xpd()
248 FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd)  in pmu_ll_lp_set_regulator_xpd()  argument
250     hw->lp_sys[mode].regulator0.xpd = xpd;  in pmu_ll_lp_set_regulator_xpd()
253 FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_sleep_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint3…  in pmu_ll_lp_set_regulator_sleep_dbias()  argument
255     hw->lp_sys[mode].regulator0.slp_dbias = slp_dbias;  in pmu_ll_lp_set_regulator_sleep_dbias()
258 FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t db…  in pmu_ll_lp_set_regulator_dbias()  argument
260     hw->lp_sys[mode].regulator0.dbias = dbias;  in pmu_ll_lp_set_regulator_dbias()
263 FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32…  in pmu_ll_lp_set_regulator_driver_bar()  argument
265     hw->lp_sys[mode].regulator1.drv_b = drv_b;  in pmu_ll_lp_set_regulator_driver_bar()
268 FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_xtal)  in pmu_ll_lp_set_xtal_xpd()  argument
271     hw->lp_sys[mode].xtal.xpd_xtal = xpd_xtal;  in pmu_ll_lp_set_xtal_xpd()
275 FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)  in pmu_ll_lp_set_dig_power()  argument
277     hw->lp_sys[mode].dig_power.val = flag;  in pmu_ll_lp_set_dig_power()
280 FORCE_INLINE_ATTR void pmu_ll_lp_set_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t xpd_flag)  in pmu_ll_lp_set_clk_power()  argument
282     hw->lp_sys[mode].clk_power.val = xpd_flag;  in pmu_ll_lp_set_clk_power()
285 FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode)  in pmu_ll_lp_get_clk_power()  argument
287     return hw->lp_sys[mode].clk_power.val;  in pmu_ll_lp_get_clk_power()
290 FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_bias)  in pmu_ll_lp_set_bias_xpd()  argument
293     hw->lp_sys[mode].bias.xpd_bias = xpd_bias;  in pmu_ll_lp_set_bias_xpd()
296 FORCE_INLINE_ATTR void pmu_ll_lp_set_dbg_atten(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)  in pmu_ll_lp_set_dbg_atten()  argument
299     hw->lp_sys[mode].bias.dbg_atten = value;  in pmu_ll_lp_set_dbg_atten()
302 FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off)  in pmu_ll_lp_set_current_power_off()  argument
305     hw->lp_sys[mode].bias.pd_cur = off;  in pmu_ll_lp_set_current_power_off()
308 FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool en)  in pmu_ll_lp_set_bias_sleep_enable()  argument
311     hw->lp_sys[mode].bias.bias_sleep = en;  in pmu_ll_lp_set_bias_sleep_enable()
316 FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag)  in pmu_ll_imm_set_clk_power()  argument
318     hw->imm.clk_power.val = flag;  in pmu_ll_imm_set_clk_power()
321 FORCE_INLINE_ATTR void pmu_ll_imm_set_icg_slp_sel(pmu_dev_t *hw, bool slp_sel)  in pmu_ll_imm_set_icg_slp_sel()  argument
324         hw->imm.sleep_sysclk.tie_high_icg_slp_sel = 1;  in pmu_ll_imm_set_icg_slp_sel()
326         hw->imm.sleep_sysclk.tie_low_icg_slp_sel = 1;  in pmu_ll_imm_set_icg_slp_sel()
330 FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_sysclk_sel(pmu_dev_t *hw, bool update)  in pmu_ll_imm_update_dig_sysclk_sel()  argument
332     hw->imm.sleep_sysclk.update_dig_sysclk_sel = update;  in pmu_ll_imm_update_dig_sysclk_sel()
335 FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_switch(pmu_dev_t *hw, bool update)  in pmu_ll_imm_update_dig_icg_switch()  argument
337     hw->imm.sleep_sysclk.update_dig_icg_switch = update;  in pmu_ll_imm_update_dig_icg_switch()
340 FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_func(pmu_dev_t *hw, bool icg_func_update)  in pmu_ll_imm_update_dig_icg_func()  argument
342     hw->imm.hp_func_icg.update_dig_icg_func_en = icg_func_update;  in pmu_ll_imm_update_dig_icg_func()
345 FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb_update)  in pmu_ll_imm_update_dig_icg_apb()  argument
347     hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update;  in pmu_ll_imm_update_dig_icg_apb()
350 FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_modem_code(pmu_dev_t *hw, bool icg_modem_update)  in pmu_ll_imm_update_dig_icg_modem_code()  argument
352     hw->imm.modem_icg.update_dig_icg_modem_en = icg_modem_update;  in pmu_ll_imm_update_dig_icg_modem_code()
355 FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel)  in pmu_ll_imm_set_lp_rootclk_sel()  argument
358         hw->imm.lp_icg.tie_high_lp_rootclk_sel = 1;  in pmu_ll_imm_set_lp_rootclk_sel()
360         hw->imm.lp_icg.tie_low_lp_rootclk_sel = 1;  in pmu_ll_imm_set_lp_rootclk_sel()
364 FORCE_INLINE_ATTR void pmu_ll_imm_set_hp_pad_hold_all(pmu_dev_t *hw, bool hold_all)  in pmu_ll_imm_set_hp_pad_hold_all()  argument
367         hw->imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;  in pmu_ll_imm_set_hp_pad_hold_all()
369         hw->imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;  in pmu_ll_imm_set_hp_pad_hold_all()
373 FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_all)  in pmu_ll_imm_set_lp_pad_hold_all()  argument
376         hw->imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;  in pmu_ll_imm_set_lp_pad_hold_all()
378         hw->imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;  in pmu_ll_imm_set_lp_pad_hold_all()
383 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain,…  in pmu_ll_hp_set_power_force_reset()  argument
385     hw->power.hp_pd[domain].force_reset = rst;  in pmu_ll_hp_set_power_force_reset()
388 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domai…  in pmu_ll_hp_set_power_force_isolate()  argument
390     hw->power.hp_pd[domain].force_iso = iso;  in pmu_ll_hp_set_power_force_isolate()
393 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t doma…  in pmu_ll_hp_set_power_force_power_up()  argument
395     hw->power.hp_pd[domain].force_pu = fpu;  in pmu_ll_hp_set_power_force_power_up()
398 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t doma…  in pmu_ll_hp_set_power_force_no_reset()  argument
400     hw->power.hp_pd[domain].force_no_reset = no_rst;  in pmu_ll_hp_set_power_force_no_reset()
403 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t do…  in pmu_ll_hp_set_power_force_no_isolate()  argument
405     hw->power.hp_pd[domain].force_no_iso = no_iso;  in pmu_ll_hp_set_power_force_no_isolate()
408 FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t do…  in pmu_ll_hp_set_power_force_power_down()  argument
410     hw->power.hp_pd[domain].force_pd = fpd;  in pmu_ll_hp_set_power_force_power_down()
413 FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)  in pmu_ll_lp_set_power_force_reset()  argument
415     hw->power.lp_peri.force_reset = rst;  in pmu_ll_lp_set_power_force_reset()
418 FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_isolate(pmu_dev_t *hw, bool iso)  in pmu_ll_lp_set_power_force_isolate()  argument
420     hw->power.lp_peri.force_iso = iso;  in pmu_ll_lp_set_power_force_isolate()
423 FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_up(pmu_dev_t *hw, bool fpu)  in pmu_ll_lp_set_power_force_power_up()  argument
425     hw->power.lp_peri.force_pu = fpu;  in pmu_ll_lp_set_power_force_power_up()
428 FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_reset(pmu_dev_t *hw, bool no_rst)  in pmu_ll_lp_set_power_force_no_reset()  argument
430     hw->power.lp_peri.force_no_reset = no_rst;  in pmu_ll_lp_set_power_force_no_reset()
433 FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_isolate(pmu_dev_t *hw, bool no_iso)  in pmu_ll_lp_set_power_force_no_isolate()  argument
435     hw->power.lp_peri.force_no_iso = no_iso;  in pmu_ll_lp_set_power_force_no_isolate()
438 FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool fpd)  in pmu_ll_lp_set_power_force_power_down()  argument
440     hw->power.lp_peri.force_pd = fpd;  in pmu_ll_lp_set_power_force_power_down()
443 FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso)  in pmu_ll_hp_set_memory_isolate()  argument
445     hw->power.mem_cntl.force_hp_mem_iso = iso;  in pmu_ll_hp_set_memory_isolate()
448 FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd)  in pmu_ll_hp_set_memory_power_down()  argument
450     hw->power.mem_cntl.force_hp_mem_pd = fpd;  in pmu_ll_hp_set_memory_power_down()
453 FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso)  in pmu_ll_hp_set_memory_no_isolate()  argument
455     hw->power.mem_cntl.force_hp_mem_no_iso = no_iso;  in pmu_ll_hp_set_memory_no_isolate()
458 FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu)  in pmu_ll_hp_set_memory_power_up()  argument
460     hw->power.mem_cntl.force_hp_mem_pu = fpu;  in pmu_ll_hp_set_memory_power_up()
464 FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)  in pmu_ll_hp_set_sleep_enable()  argument
466     hw->wakeup.cntl0.sleep_req = 1;  in pmu_ll_hp_set_sleep_enable()
469 FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_enable(pmu_dev_t *hw, uint32_t reject)  in pmu_ll_hp_set_reject_enable()  argument
471     hw->wakeup.cntl1.sleep_reject_ena = reject;  in pmu_ll_hp_set_reject_enable()
472     hw->wakeup.cntl1.slp_reject_en = 1;  in pmu_ll_hp_set_reject_enable()
475 FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw)  in pmu_ll_hp_set_reject_disable()  argument
477     hw->wakeup.cntl1.slp_reject_en = 0;  in pmu_ll_hp_set_reject_disable()
480 FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)  in pmu_ll_hp_set_wakeup_enable()  argument
482     hw->wakeup.cntl2 = wakeup;  in pmu_ll_hp_set_wakeup_enable()
485 FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode)  in pmu_ll_hp_set_sleep_protect_mode()  argument
487     hw->wakeup.cntl3.sleep_prt_sel = mode;  in pmu_ll_hp_set_sleep_protect_mode()
490 FORCE_INLINE_ATTR void pmu_ll_hp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)  in pmu_ll_hp_set_min_sleep_cycle()  argument
492     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, hp_min_slp_val, slow_clk_cycle);  in pmu_ll_hp_set_min_sleep_cycle()
495 FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_cause(pmu_dev_t *hw)  in pmu_ll_hp_clear_reject_cause()  argument
497     hw->wakeup.cntl4.slp_reject_cause_clr = 1;  in pmu_ll_hp_clear_reject_cause()
500 FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_wakeup(pmu_dev_t *hw)  in pmu_ll_hp_is_sleep_wakeup()  argument
502     return (hw->hp_ext.int_raw.wakeup == 1);  in pmu_ll_hp_is_sleep_wakeup()
505 FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw)  in pmu_ll_hp_is_sleep_reject()  argument
507     return (hw->hp_ext.int_raw.reject == 1);  in pmu_ll_hp_is_sleep_reject()
510 FORCE_INLINE_ATTR void pmu_ll_hp_clear_sw_intr_status(pmu_dev_t *hw)  in pmu_ll_hp_clear_sw_intr_status()  argument
512     hw->hp_ext.int_clr.sw = 1;  in pmu_ll_hp_clear_sw_intr_status()
515 FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw)  in pmu_ll_hp_clear_wakeup_intr_status()  argument
517     hw->hp_ext.int_clr.wakeup = 1;  in pmu_ll_hp_clear_wakeup_intr_status()
520 FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)  in pmu_ll_hp_clear_reject_intr_status()  argument
522     hw->hp_ext.int_clr.reject = 1;  in pmu_ll_hp_clear_reject_intr_status()
525 FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)  in pmu_ll_hp_get_wakeup_cause()  argument
527     return hw->wakeup.status0;  in pmu_ll_hp_get_wakeup_cause()
530 FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw)  in pmu_ll_hp_get_reject_cause()  argument
532     return hw->wakeup.status1;  in pmu_ll_hp_get_reject_cause()
535 FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_interrupt_raw(pmu_dev_t *hw)  in pmu_ll_lp_get_interrupt_raw()  argument
537     return hw->lp_ext.int_raw.val;  in pmu_ll_lp_get_interrupt_raw()
540 FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask)  in pmu_ll_lp_clear_intsts_mask()  argument
542     hw->lp_ext.int_clr.val = mask;  in pmu_ll_lp_clear_intsts_mask()
545 FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)  in pmu_ll_lp_set_min_sleep_cycle()  argument
547     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, lp_min_slp_val, slow_clk_cycle);  in pmu_ll_lp_set_min_sleep_cycle()
550 FORCE_INLINE_ATTR void pmu_ll_hp_set_modify_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_hp_set_modify_icg_cntl_wait_cycle()  argument
552     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait, cycle);  in pmu_ll_hp_set_modify_icg_cntl_wait_cycle()
555 FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_modify_icg_cntl_wait_cycle(pmu_dev_t *hw)  in pmu_ll_hp_get_modify_icg_cntl_wait_cycle()  argument
557     return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait);  in pmu_ll_hp_get_modify_icg_cntl_wait_cycle()
560 FORCE_INLINE_ATTR void pmu_ll_hp_set_switch_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_hp_set_switch_icg_cntl_wait_cycle()  argument
562     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait, cycle);  in pmu_ll_hp_set_switch_icg_cntl_wait_cycle()
565 FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_switch_icg_cntl_wait_cycle(pmu_dev_t *hw)  in pmu_ll_hp_get_switch_icg_cntl_wait_cycle()  argument
567     return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait);  in pmu_ll_hp_get_switch_icg_cntl_wait_cycle()
570 FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_hp_set_digital_power_down_wait_cycle()  argument
572     hw->power.wait_timer0.powerdown_timer = cycle;  in pmu_ll_hp_set_digital_power_down_wait_cycle()
575 FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)  in pmu_ll_hp_get_digital_power_down_wait_cycle()  argument
577     return hw->power.wait_timer0.powerdown_timer;  in pmu_ll_hp_get_digital_power_down_wait_cycle()
580 FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_lp_set_digital_power_down_wait_cycle()  argument
582     hw->power.wait_timer1.powerdown_timer = cycle;  in pmu_ll_lp_set_digital_power_down_wait_cycle()
585 FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)  in pmu_ll_lp_get_digital_power_down_wait_cycle()  argument
587     return hw->power.wait_timer1.powerdown_timer;  in pmu_ll_lp_get_digital_power_down_wait_cycle()
590 FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycl…  in pmu_ll_lp_set_analog_wait_target_cycle()  argument
592     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target, slow_clk_cycle);  in pmu_ll_lp_set_analog_wait_target_cycle()
595 FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw)  in pmu_ll_lp_get_analog_wait_target_cycle()  argument
597     return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target);  in pmu_ll_lp_get_analog_wait_target_cycle()
600 FORCE_INLINE_ATTR void pmu_ll_set_modem_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_set_modem_wait_target_cycle()  argument
602     hw->wakeup.cntl5.modem_wait_target = cycle;  in pmu_ll_set_modem_wait_target_cycle()
605 FORCE_INLINE_ATTR uint32_t pmu_ll_get_modem_wait_target_cycle(pmu_dev_t *hw)  in pmu_ll_get_modem_wait_target_cycle()  argument
607     return hw->wakeup.cntl5.modem_wait_target;  in pmu_ll_get_modem_wait_target_cycle()
610 FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_set_xtal_stable_wait_cycle()  argument
612     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable, cycle);  in pmu_ll_set_xtal_stable_wait_cycle()
615 FORCE_INLINE_ATTR uint32_t pmu_ll_get_xtal_stable_wait_cycle(pmu_dev_t *hw)  in pmu_ll_get_xtal_stable_wait_cycle()  argument
617     return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable);  in pmu_ll_get_xtal_stable_wait_cycle()
620 FORCE_INLINE_ATTR void pmu_ll_set_pll_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_set_pll_stable_wait_cycle()  argument
622     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable, cycle);  in pmu_ll_set_pll_stable_wait_cycle()
625 FORCE_INLINE_ATTR uint32_t pmu_ll_get_pll_stable_wait_cycle(pmu_dev_t *hw)  in pmu_ll_get_pll_stable_wait_cycle()  argument
627     return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable);  in pmu_ll_get_pll_stable_wait_cycle()
630 FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_lp_set_digital_power_supply_wait_cycle()  argument
632     hw->power.wait_timer1.wait_timer = cycle;  in pmu_ll_lp_set_digital_power_supply_wait_cycle()
635 FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)  in pmu_ll_lp_get_digital_power_supply_wait_cycle()  argument
637     return hw->power.wait_timer1.wait_timer;  in pmu_ll_lp_get_digital_power_supply_wait_cycle()
640 FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_lp_set_digital_power_up_wait_cycle()  argument
642     hw->power.wait_timer1.powerup_timer = cycle;  in pmu_ll_lp_set_digital_power_up_wait_cycle()
645 FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)  in pmu_ll_lp_get_digital_power_up_wait_cycle()  argument
647     return hw->power.wait_timer1.powerup_timer;  in pmu_ll_lp_get_digital_power_up_wait_cycle()
650 FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_hp_set_analog_wait_target_cycle()  argument
652     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle);  in pmu_ll_hp_set_analog_wait_target_cycle()
655 FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw)  in pmu_ll_hp_get_analog_wait_target_cycle()  argument
657     return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target);  in pmu_ll_hp_get_analog_wait_target_cycle()
660 FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_hp_set_digital_power_supply_wait_cycle()  argument
662     hw->power.wait_timer0.wait_timer = cycle;  in pmu_ll_hp_set_digital_power_supply_wait_cycle()
665 FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)  in pmu_ll_hp_get_digital_power_supply_wait_cycle()  argument
667     return hw->power.wait_timer0.wait_timer;  in pmu_ll_hp_get_digital_power_supply_wait_cycle()
670 FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)  in pmu_ll_hp_set_digital_power_up_wait_cycle()  argument
672     hw->power.wait_timer0.powerup_timer = cycle;  in pmu_ll_hp_set_digital_power_up_wait_cycle()
675 FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)  in pmu_ll_hp_get_digital_power_up_wait_cycle()  argument
677     return hw->power.wait_timer0.powerup_timer;  in pmu_ll_hp_get_digital_power_up_wait_cycle()
680 FORCE_INLINE_ATTR uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw)  in pmu_ll_get_sysclk_sleep_select_state()  argument
682     return hw->clk_state0.sysclk_slp_sel;  in pmu_ll_get_sysclk_sleep_select_state()