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Searched refs:cfg (Results 1 – 25 of 154) sorted by relevance

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/hal_espressif-latest/components/hal/
Dspi_flash_hal.c24 static uint32_t get_flash_clock_divider(const spi_flash_hal_config_t *cfg) in get_flash_clock_divider() argument
26 int clk_source = cfg->clock_src_freq; in get_flash_clock_divider()
33 if (clk_source < cfg->freq_mhz) { in get_flash_clock_divider()
34 HAL_LOGE(TAG, "Target frequency %dMHz higher than supported.", cfg->freq_mhz); in get_flash_clock_divider()
38 if (cfg->freq_mhz == 26 || cfg->freq_mhz == 27) { in get_flash_clock_divider()
43 best_div = (int)DIV_ROUND_UP((double)clk_source, (double)cfg->freq_mhz); in get_flash_clock_divider()
44 if ((cfg->clock_src_freq % cfg->freq_mhz) != 0) { in get_flash_clock_divider()
52 static uint32_t spi_flash_cal_clock(const spi_flash_hal_config_t *cfg) in spi_flash_cal_clock() argument
54 …nt32_t div_parameter = spi_flash_ll_calculate_clock_reg(cfg->host_id, get_flash_clock_divider(cfg)… in spi_flash_cal_clock()
75 static inline int extra_dummy_under_timing_tuning(const spi_flash_hal_config_t *cfg) in extra_dummy_under_timing_tuning() argument
[all …]
Dbrownout_hal.c11 void brownout_hal_config(const brownout_hal_config_t *cfg) in brownout_hal_config() argument
16 brownout_ll_enable_flash_power_down(cfg->flash_power_down); in brownout_hal_config()
17 brownout_ll_enable_rf_power_down(cfg->rf_power_down); in brownout_hal_config()
19 brownout_ll_reset_config(cfg->reset_enabled, 0x3ff, 1); in brownout_hal_config()
20 brownout_ll_set_threshold(cfg->threshold); in brownout_hal_config()
21 brownout_ll_bod_enable(cfg->enabled); in brownout_hal_config()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Drtc_sleep.c30 void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) in rtc_sleep_pu() argument
32 REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); in rtc_sleep_pu()
33 REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu); in rtc_sleep_pu()
34 REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu); in rtc_sleep_pu()
35 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pu()
36 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pu()
37 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pu()
38 REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu); in rtc_sleep_pu()
39 REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu); in rtc_sleep_pu()
40 REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu); in rtc_sleep_pu()
[all …]
Drtc_clk_init.c22 void rtc_clk_init(rtc_clk_config_t cfg) in rtc_clk_init() argument
34 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); in rtc_clk_init()
35 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
38 rtc_clk_divider_set(cfg.clk_rtc_clk_div); in rtc_clk_init()
41 rtc_clk_8m_divider_set(cfg.clk_8m_clk_div); in rtc_clk_init()
48 rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; in rtc_clk_init()
56 bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); in rtc_clk_init()
64 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); in rtc_clk_init()
71 if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { in rtc_clk_init()
73 } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { in rtc_clk_init()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32c2/
Drtc_sleep.c31 void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) in rtc_sleep_pu() argument
33 REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); in rtc_sleep_pu()
34 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pu()
35 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pu()
36 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pu()
37 REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu); in rtc_sleep_pu()
38 REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu); in rtc_sleep_pu()
39 REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu); in rtc_sleep_pu()
40 REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu); in rtc_sleep_pu()
41 REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu); in rtc_sleep_pu()
[all …]
Drtc_clk_init.c25 void rtc_clk_init(rtc_clk_config_t cfg) in rtc_clk_init() argument
37 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); in rtc_clk_init()
38 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
41 rtc_clk_divider_set(cfg.clk_rtc_clk_div); in rtc_clk_init()
44 rtc_clk_8m_divider_set(cfg.clk_8m_clk_div); in rtc_clk_init()
51 rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; in rtc_clk_init()
59 bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); in rtc_clk_init()
67 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); in rtc_clk_init()
74 if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { in rtc_clk_init()
78 rtc_clk_fast_src_set(cfg.fast_clk_src); in rtc_clk_init()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32s2/
Drtc_sleep.c27 void rtc_sleep_pd(rtc_sleep_pd_config_t cfg) in rtc_sleep_pd() argument
29 REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); in rtc_sleep_pd()
30 REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu); in rtc_sleep_pd()
31 REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu); in rtc_sleep_pd()
32 REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, cfg.i2s_fpu); in rtc_sleep_pd()
33 REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, cfg.i2s_fpu); in rtc_sleep_pd()
34 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pd()
35 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pd()
36 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pd()
37 REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu); in rtc_sleep_pd()
[all …]
Drtc_clk_init.c24 void rtc_clk_init(rtc_clk_config_t cfg) in rtc_clk_init() argument
36 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); in rtc_clk_init()
37 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
40 rtc_clk_divider_set(cfg.clk_rtc_clk_div); in rtc_clk_init()
43 rtc_clk_8m_divider_set(cfg.clk_8m_clk_div); in rtc_clk_init()
51 rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; in rtc_clk_init()
58 bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); in rtc_clk_init()
66 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); in rtc_clk_init()
73 if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { in rtc_clk_init()
75 } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { in rtc_clk_init()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
Drtc_sleep.c37 void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) in rtc_sleep_pu() argument
39 REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); in rtc_sleep_pu()
40 REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu); in rtc_sleep_pu()
41 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pu()
42 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pu()
43 REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu); in rtc_sleep_pu()
44 REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu); in rtc_sleep_pu()
45 REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu); in rtc_sleep_pu()
46 REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu); in rtc_sleep_pu()
47 REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu); in rtc_sleep_pu()
[all …]
Drtc_clk_init.c25 void rtc_clk_init(rtc_clk_config_t cfg) in rtc_clk_init() argument
37 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); in rtc_clk_init()
38 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
41 rtc_clk_divider_set(cfg.clk_rtc_clk_div); in rtc_clk_init()
44 rtc_clk_8m_divider_set(cfg.clk_8m_clk_div); in rtc_clk_init()
51 rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; in rtc_clk_init()
59 bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); in rtc_clk_init()
67 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); in rtc_clk_init()
74 if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { in rtc_clk_init()
76 } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { in rtc_clk_init()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32/
Drtc_sleep.c68 static void rtc_sleep_pd(rtc_sleep_pd_config_t cfg) in rtc_sleep_pd() argument
70 REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, ~cfg.dig_pd); in rtc_sleep_pd()
71 REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, ~cfg.rtc_pd); in rtc_sleep_pd()
72 REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, ~cfg.rtc_pd); in rtc_sleep_pd()
73 DPORT_REG_SET_FIELD(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK, ~cfg.cpu_pd); in rtc_sleep_pd()
74 REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, ~cfg.i2s_pd); in rtc_sleep_pd()
75 REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, ~cfg.i2s_pd); in rtc_sleep_pd()
76 REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, ~cfg.bb_pd); in rtc_sleep_pd()
77 REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, ~cfg.bb_pd); in rtc_sleep_pd()
78 REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, ~cfg.nrx_pd); in rtc_sleep_pd()
[all …]
Drtc_clk_init.c32 void rtc_clk_init(rtc_clk_config_t cfg) in rtc_clk_init() argument
61 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); in rtc_clk_init()
62 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
65 clk_ll_rc_fast_set_divider(cfg.clk_8m_div + 1); in rtc_clk_init()
74 rtc_xtal_freq_t configured_xtal_freq = cfg.xtal_freq; in rtc_clk_init()
110 bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); in rtc_clk_init()
124 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); in rtc_clk_init()
131 if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { in rtc_clk_init()
133 } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { in rtc_clk_init()
137 rtc_clk_fast_src_set(cfg.fast_clk_src); in rtc_clk_init()
[all …]
/hal_espressif-latest/components/driver/deprecated/esp32s2/
Ddac_legacy.c58 esp_err_t dac_digi_controller_config(const dac_digi_config_t *cfg) in dac_digi_controller_config() argument
60 ESP_RETURN_ON_FALSE(cfg->mode <= DAC_CONV_ALTER, ESP_ERR_INVALID_ARG, TAG, "DAC mode error"); in dac_digi_controller_config()
61 …ESP_RETURN_ON_FALSE(cfg->interval > 0 && cfg->interval < 4096, ESP_ERR_INVALID_ARG, TAG, "DAC inte… in dac_digi_controller_config()
62 …ESP_RETURN_ON_FALSE(cfg->dig_clk.div_num < 256, ESP_ERR_INVALID_ARG, TAG, "DAC clk div_num error"); in dac_digi_controller_config()
63 …ESP_RETURN_ON_FALSE(cfg->dig_clk.div_b > 0 && cfg->dig_clk.div_b < 64, ESP_ERR_INVALID_ARG, TAG, "… in dac_digi_controller_config()
64 ESP_RETURN_ON_FALSE(cfg->dig_clk.div_a < 64, ESP_ERR_INVALID_ARG, TAG, "DAC clk div_a error"); in dac_digi_controller_config()
68 if (cfg->dig_clk.use_apll) { in dac_digi_controller_config()
82 dac_ll_digi_set_convert_mode(cfg->mode == DAC_CONV_ALTER); in dac_digi_controller_config()
83 dac_ll_digi_set_trigger_interval(cfg->interval); in dac_digi_controller_config()
84 adc_ll_digi_controller_clk_div(cfg->dig_clk.div_num, cfg->dig_clk.div_b, cfg->dig_clk.div_a); in dac_digi_controller_config()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32h2/
Drtc_clk_init.c28 void rtc_clk_init(rtc_clk_config_t cfg) in rtc_clk_init() argument
41 REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
42 REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_SCK_DCAP, cfg.slow_clk_dcap); in rtc_clk_init()
43 REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq); in rtc_clk_init()
56 rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; in rtc_clk_init()
63 bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); in rtc_clk_init()
71 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); in rtc_clk_init()
77 if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { in rtc_clk_init()
79 } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { in rtc_clk_init()
81 } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { in rtc_clk_init()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32c6/
Drtc_clk_init.c59 void rtc_clk_init(rtc_clk_config_t cfg) in rtc_clk_init() argument
74 REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
75 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, cfg.slow_clk_dcap); in rtc_clk_init()
76 REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq); in rtc_clk_init()
89 rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; in rtc_clk_init()
101 bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); in rtc_clk_init()
109 esp_cpu_set_cycle_count( (uint64_t)esp_cpu_get_cycle_count() * cfg.cpu_freq_mhz / freq_before ); in rtc_clk_init()
115 if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { in rtc_clk_init()
117 } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { in rtc_clk_init()
119 } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { in rtc_clk_init()
[all …]
/hal_espressif-latest/components/bt/host/bluedroid/stack/avdt/
Davdt_l2c.c79 tL2CAP_CFG_INFO cfg; in avdt_sec_check_complete_term() local
108 memset(&cfg, 0, sizeof(tL2CAP_CFG_INFO)); in avdt_sec_check_complete_term()
109 cfg.mtu_present = TRUE; in avdt_sec_check_complete_term()
110 cfg.mtu = p_tbl->my_mtu; in avdt_sec_check_complete_term()
111 cfg.flush_to_present = TRUE; in avdt_sec_check_complete_term()
112 cfg.flush_to = p_tbl->my_flush_to; in avdt_sec_check_complete_term()
113 L2CA_ConfigReq(p_tbl->lcid, &cfg); in avdt_sec_check_complete_term()
134 tL2CAP_CFG_INFO cfg; in avdt_sec_check_complete_orig() local
152 memset(&cfg, 0, sizeof(tL2CAP_CFG_INFO)); in avdt_sec_check_complete_orig()
153 cfg.mtu_present = TRUE; in avdt_sec_check_complete_orig()
[all …]
/hal_espressif-latest/components/wpa_supplicant/src/wps/
Dwps.c39 struct wps_data * wps_init(const struct wps_config *cfg) in wps_init() argument
44 data->wps = cfg->wps; in wps_init()
45 data->registrar = cfg->registrar; in wps_init()
46 if (cfg->registrar) { in wps_init()
47 os_memcpy(data->uuid_r, cfg->wps->uuid, WPS_UUID_LEN); in wps_init()
49 os_memcpy(data->mac_addr_e, cfg->wps->dev.mac_addr, ETH_ALEN); in wps_init()
50 os_memcpy(data->uuid_e, cfg->wps->uuid, WPS_UUID_LEN); in wps_init()
52 if (cfg->pbc == 0 && cfg->pin_len) { in wps_init()
53 data->dev_pw_id = cfg->dev_pw_id; in wps_init()
54 data->dev_password = os_memdup(cfg->pin, cfg->pin_len); in wps_init()
[all …]
/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_common.c90 rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config(); in bootloader_common_vddsdio_configure() local
91 …if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) { // VDDSDIO regulator is enabled @ 1… in bootloader_common_vddsdio_configure()
92 cfg.drefh = 3; in bootloader_common_vddsdio_configure()
93 cfg.drefm = 3; in bootloader_common_vddsdio_configure()
94 cfg.drefl = 3; in bootloader_common_vddsdio_configure()
95 cfg.force = 1; in bootloader_common_vddsdio_configure()
96 rtc_vddsdio_set_config(cfg); in bootloader_common_vddsdio_configure()
/hal_espressif-latest/components/bt/host/bluedroid/stack/sdp/
Dsdp_main.c270 tL2CAP_CFG_INFO cfg = sdp_cb.l2cap_my_cfg; in sdp_connect_ind() local
272 if (cfg.fcr_present) { in sdp_connect_ind()
274 cfg.fcr.mode, cfg.fcr.tx_win_sz, cfg.fcr.max_transmit, in sdp_connect_ind()
275 cfg.fcr.rtrans_tout, cfg.fcr.mon_tout, cfg.fcr.mps); in sdp_connect_ind()
278 if ((!L2CA_ConfigReq (l2cap_cid, &cfg)) && cfg.fcr_present in sdp_connect_ind()
279 && cfg.fcr.mode != L2CAP_FCR_BASIC_MODE) { in sdp_connect_ind()
281 cfg.fcr.mode = L2CAP_FCR_BASIC_MODE; in sdp_connect_ind()
282 cfg.fcr_present = FALSE; in sdp_connect_ind()
283 L2CA_ConfigReq (l2cap_cid, &cfg); in sdp_connect_ind()
309 tL2CAP_CFG_INFO cfg; in sdp_connect_cfm() local
[all …]
/hal_espressif-latest/tools/esptool_py/esptool/
Dconfig.py31 cfg = configparser.RawConfigParser()
33 cfg.read(file_path, encoding="UTF-8")
35 if cfg.has_section("esptool"):
37 unknown_opts = list(set(cfg.options("esptool")) - set(CONFIG_OPTIONS))
81 cfg = configparser.ConfigParser()
82 cfg["esptool"] = {} # Create an empty esptool config for when no file is found
86 cfg.read(cfg_file_path)
93 return cfg, cfg_file_path
/hal_espressif-latest/components/driver/deprecated/
Dadc_i2s_deprecated.c149 static void adc_digi_controller_reg_set(const adc_digi_config_t *cfg) in adc_digi_controller_reg_set() argument
152 switch (cfg->conv_mode) { in adc_digi_controller_reg_set()
169 if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) { in adc_digi_controller_reg_set()
171 if (cfg->adc1_pattern_len) { in adc_digi_controller_reg_set()
173 adc_ll_digi_set_pattern_table_len(ADC_UNIT_1, cfg->adc1_pattern_len); in adc_digi_controller_reg_set()
174 for (uint32_t i = 0; i < cfg->adc1_pattern_len; i++) { in adc_digi_controller_reg_set()
175 adc_ll_digi_prepare_pattern_table(ADC_UNIT_1, i, cfg->adc1_pattern[i]); in adc_digi_controller_reg_set()
179 if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_2) { in adc_digi_controller_reg_set()
181 if (cfg->adc2_pattern_len) { in adc_digi_controller_reg_set()
183 adc_ll_digi_set_pattern_table_len(ADC_UNIT_2, cfg->adc2_pattern_len); in adc_digi_controller_reg_set()
[all …]
/hal_espressif-latest/components/esp_system/port/
Dbrownout.c70 brownout_hal_config_t cfg = { in esp_brownout_init() local
78 brownout_hal_config(&cfg); in esp_brownout_init()
91 brownout_hal_config_t cfg = { in esp_brownout_init()
99 brownout_hal_config(&cfg); in esp_brownout_init()
105 brownout_hal_config_t cfg = { in esp_brownout_disable() local
109 brownout_hal_config(&cfg); in esp_brownout_disable()
/hal_espressif-latest/components/bt/esp_ble_mesh/mesh_core/
Dcfg_srv.c694 struct bt_mesh_cfg_srv *cfg = model->user_data; in beacon_set() local
700 if (!cfg) { in beacon_set()
703 if (buf->data[0] != cfg->beacon) { in beacon_set()
704 cfg->beacon = buf->data[0]; in beacon_set()
710 if (cfg->beacon) { in beacon_set()
752 struct bt_mesh_cfg_srv *cfg = model->user_data; in default_ttl_set() local
758 if (!cfg) { in default_ttl_set()
761 if (cfg->default_ttl != buf->data[0]) { in default_ttl_set()
762 cfg->default_ttl = buf->data[0]; in default_ttl_set()
809 struct bt_mesh_cfg_srv *cfg = model->user_data; in gatt_proxy_set() local
[all …]
/hal_espressif-latest/components/esp_adc/
Dadc_filter.c49 …if (atomic_compare_exchange_strong(&s_adc_filter_claimed[filter_ctx->cfg.unit], &true_var, false))… in s_adc_filter_free()
107 filter_ctx->cfg.unit = config->unit; in adc_new_continuous_iir_filter()
108 filter_ctx->cfg.channel = config->channel; in adc_new_continuous_iir_filter()
109 filter_ctx->cfg.coeff = config->coeff; in adc_new_continuous_iir_filter()
128 adc_ll_digi_filter_reset(filter_hdl->filter_id, filter_hdl->cfg.unit); in adc_continuous_iir_filter_enable()
129 …lter_set_factor(filter_hdl->filter_id, filter_hdl->cfg.unit, filter_hdl->cfg.channel, filter_hdl->… in adc_continuous_iir_filter_enable()
130 adc_ll_digi_filter_enable(filter_hdl->filter_id, filter_hdl->cfg.unit, true); in adc_continuous_iir_filter_enable()
142 adc_ll_digi_filter_enable(filter_hdl->filter_id, filter_hdl->cfg.unit, false); in adc_continuous_iir_filter_disable()
/hal_espressif-latest/components/hal/esp32c2/
Drtc_cntl_hal.c18 uint32_t cfg[4]; /* 4 word for dma link buffer configuration */ member
48 pbuf->cfg[0] = 0; in rtc_cntl_hal_enable_cpu_retention()
49 pbuf->cfg[1] = 0; in rtc_cntl_hal_enable_cpu_retention()
50 pbuf->cfg[2] = 0; in rtc_cntl_hal_enable_cpu_retention()
51 pbuf->cfg[3] = (uint32_t)-1; in rtc_cntl_hal_enable_cpu_retention()

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