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/hal_espressif-latest/components/xtensa/include/
Dxt_instr_macros.h11 #define RSR(reg, at) __asm__ volatile ("rsr %0, %1" : "=r" (at) : "i" (reg)) argument
12 #define WSR(reg, at) __asm__ volatile ("wsr %0, %1" : : "r" (at), "i" (reg)) argument
13 #define XSR(reg, at) __asm__ volatile ("xsr %0, %1" : "+r" (at) : "i" (reg)) argument
15 #define RER(reg, at) __asm__ volatile ("rer %0, %1" : "=r" (at) : "r" (reg)) argument
17 #define WITLB(at, as) __asm__ volatile ("witlb %0, %1; \n isync \n " : : "r" (at), "r" (as)) argument
18 #define WDTLB(at, as) __asm__ volatile ("wdtlb %0, %1; \n dsync \n " : : "r" (at), "r" (as)) argument
/hal_espressif-latest/components/xtensa/include/xtensa/
Dcoreasm.h87 .macro find_ms_setbit ad, as, at, base
89 movi \at, 31+\base
91 sub \ad, \at, \as // get numbering from lsbit (0..31, -1 if absent)
93 movi \at, \base // start with result of 0 (point to lsbit of 32)
97 addi \at, \at, 16 // no, increment result to upper 16 bits (of 32)
101 addi \at, \at, 8 // no, increment result to upper 8 bits (of 16)
104 addi \at, \at, 4 // no, increment result to upper 4 bits (of 8)
107 addi \at, \at, 2 // no, increment result to upper 2 bits (of 4)
110 addi \at, \at, 2 // no, increment result to upper bit (of 2)
111 2: addi \at, \at, -1 // (from just above: add 1; from beqz: return -1)
[all …]
Dcacheasm.h507 .macro cache_coherence_on ar at
512 movi \at, MEMCTL_SNOOP_EN
513 or \ar, \ar, \at
518 movi \at, XER_CCON
519 wer \ar, \at
541 .macro cache_coherence_off ar at
546 movi \at, ~MEMCTL_SNOOP_EN
547 and \ar, \ar, \at
552 movi \at, 0
554 wer \at, \ar
Dhal.h1152 uint32_t at; /* access rights, and memory type (and space for entry index) */ member
1188 #define XTHAL_MPU_ENTRY_GET_ACCESS(x) ((((x).at) >> 8) & 0xf)
1190 #define XTHAL_MPU_ENTRY_SET_ACCESS(x, accessRights) ((x).at = \
1191 ((x).at & 0xfffff0ff) | (((accessRights) & 0xf) << 8))
1193 #define XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(x) ((((x).at) >> 12) & 0x1ff)
1195 #define XTHAL_MPU_ENTRY_SET_MEMORY_TYPE(x, memtype) ((x).at = \
1196 ((x).at & 0xffe00fff) | (((XTHAL_ENCODE_MEMORY_TYPE(memtype)) & 0x1ff) << 12))
/hal_espressif-latest/components/efuse/esp32c6/
Desp_efuse_table.csv125 … 80, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected…
146 …output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at…
178 ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 145, 10, [] ADC1 init code at atten0
179 ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 155, 10, [] ADC1 init code at atten1
180 ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 165, 10, [] ADC1 init code at atten2
181 ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 175, 10, [] ADC1 init code at atten3
182 …VOL_ATTEN0, EFUSE_BLK2, 185, 10, [] ADC1 calibration voltage at atten0
183 …VOL_ATTEN1, EFUSE_BLK2, 195, 10, [] ADC1 calibration voltage at atten1
184 …VOL_ATTEN2, EFUSE_BLK2, 205, 10, [] ADC1 calibration voltage at atten2
185 …VOL_ATTEN3, EFUSE_BLK2, 215, 10, [] ADC1 calibration voltage at atten3
[all …]
/hal_espressif-latest/components/efuse/esp32s3/
Desp_efuse_table.csv173 …tput mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at…
216 …VOL_ATTEN3, EFUSE_BLK1, 186, 6, [] ADC2 calibration voltage at atten3
221 ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, [] ADC1 init code at atten0
222 ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, [] ADC1 init code at atten1
223 ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, [] ADC1 init code at atten2
224 ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, [] ADC1 init code at atten3
225 ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, [] ADC2 init code at atten0
226 ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, [] ADC2 init code at atten1
227 ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, [] ADC2 init code at atten2
228 ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, [] ADC2 init code at atten3
[all …]
/hal_espressif-latest/components/esp_pm/
DKconfig15 bool "Enable dynamic frequency scaling (DFS) at startup"
55 longer for 760us at most each time.
64 longer for 40us at most each time.
69 bool "Disable all GPIO when chip at sleep"
72 … This feature is intended to disable all GPIO pins at automantic sleep to get a lower power mode.
73 …If enabled, chips will disable all GPIO pins at automantic sleep to reduce about 200~300 uA curren…
77 to have a different GPIO configuration at sleep.
79 at first, otherwise you will not be able to switch pullup/pulldown mode.
118 … current consumption by about 100 uA. Chip will save/restore register context at sleep/wake
121 … context of the necessary hardware for FreeRTOS to run, it will need at least 4.55 KB free heap
[all …]
/hal_espressif-latest/components/log/
DKconfig8 You can set lower verbosity level at runtime using
14 at runtime will not be possible. To allow increasing log
15 level above the default at runtime, see the next option.
45 at runtime by calling esp_log_level_set(). This level may be higher than
48 This can be used enable debugging output only at a critical point, for a particular
56 fixed at compile time to the separate "Bootloader log verbosity" setting.
DREADME.rst23 …XIMUM_LEVEL`. To increase log level for a specific file above this maximum at compile time, use th…
57 To override default verbosity level at file or component scope, define the ``LOG_LOCAL_LEVEL`` macr…
72 To configure logging output per module at runtime, add calls to the function :cpp:func:`esp_log_lev…
82 … log verbosity. These macros will always log at the "default" verbosity level, which can only be c…
/hal_espressif-latest/components/esp_system/
DREADME.md9 Time with the origin at `g_startup_time`. The implementation is not handled by `esp_system`,
13 should maintain the definition of having the origin point at `g_startup_time`.
18 is at the point where the underlying timer starts counting.
/hal_espressif-latest/tools/esptool_py/docs/
DREADME.md5 The sources do not render well in GitHub and some information is not visible at all.
17 …f available options. For more information see the `esp-docs` documentation at https://github.com/e…
/hal_espressif-latest/tools/esptool_py/docs/en/espefuse/
Dset-flash-voltage-cmd.rst12 …egulator to either 1.8V, 3.3V or OFF. This means a GPIO can be high or low at reset without changi…
34 | Low or unconnected | Enabled at 3.3V |
36 | High | Enabled at 1.8V |
72 * {IDF_TARGET_VDD_SPI} regulator always enables at 1.8V.
86 * {IDF_TARGET_VDD_SPI} regulator always enables at 3.3V.
/hal_espressif-latest/components/esp_hw_support/port/esp32c6/
DKconfig.rtc13 bool "External 32kHz oscillator at 32K_XP pin"
26 Internal RC32K clock is unstable at extreme temperatures and is not recommended for use.
42 When this option is set to 0, clock calibration will not be performed at
/hal_espressif-latest/tools/esptool_py/docs/en/espefuse/inc/
Dsummary_ESP32-C3.rst20 …ADC1_INIT_CODE_ATTEN0 (BLOCK2) ADC1 init code at atten0 …
21 …ADC1_INIT_CODE_ATTEN1 (BLOCK2) ADC1 init code at atten1 …
22 …ADC1_INIT_CODE_ATTEN2 (BLOCK2) ADC1 init code at atten2 …
23 …ADC1_INIT_CODE_ATTEN3 (BLOCK2) ADC1 init code at atten3 …
24 …ADC1_CAL_VOL_ATTEN0 (BLOCK2) ADC1 calibration voltage at atten0 …
25 …ADC1_CAL_VOL_ATTEN1 (BLOCK2) ADC1 calibration voltage at atten1 …
26 …ADC1_CAL_VOL_ATTEN2 (BLOCK2) ADC1 calibration voltage at atten2 …
27 …ADC1_CAL_VOL_ATTEN3 (BLOCK2) ADC1 calibration voltage at atten3 …
/hal_espressif-latest/tools/esptool_py/docs/en/
Dresources.rst23 Mastering the Basics of Espressif Chips: An In-Depth Look at Chip Flashing
28 It offers an in-depth look at the inner mechanisms of esptool.py, including the :ref:`boot-mode` pr…
31 :alt: Mastering the Basics of Espressif Chips: An In-Depth Look at Chip Flashing
/hal_espressif-latest/components/efuse/esp32c3/
Desp_efuse_table.csv138 …output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at…
176 ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, [] ADC1 init code at atten0
177 ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, [] ADC1 init code at atten1
178 ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, [] ADC1 init code at atten2
179 ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, [] ADC1 init code at atten3
180 …VOL_ATTEN0, EFUSE_BLK2, 188, 10, [] ADC1 calibration voltage at atten0
181 …VOL_ATTEN1, EFUSE_BLK2, 198, 10, [] ADC1 calibration voltage at atten1
182 …VOL_ATTEN2, EFUSE_BLK2, 208, 10, [] ADC1 calibration voltage at atten2
183 …VOL_ATTEN3, EFUSE_BLK2, 218, 10, [] ADC1 calibration voltage at atten3
/hal_espressif-latest/components/efuse/esp32c2/
Desp_efuse_table.csv68 …output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at…
94 ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 78, 8, [] ADC1 init code at atten0
95 ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 86, 5, [] ADC1 init code at atten3
96 …VOL_ATTEN0, EFUSE_BLK2, 91, 8, [] ADC1 calibration voltage at atten0
97 …VOL_ATTEN3, EFUSE_BLK2, 99, 6, [] ADC1 calibration voltage at atten3
/hal_espressif-latest/tools/esptool_py/docs/en/esptool/
Dserial-connection.rst47 …DF_TARGET_NAME}. If you encounter any problems when connecting, please use at least 115200 or high…
53 …ader uses. The apps on top of the Espressif SDK (e.g. Arduino sketch) talk at 115200 if not specif…
Dflash-modes.rst16 A header at the beginning of a bootable image contains these values.
24 …_TARGET_NAME} at offset {IDF_TARGET_BOOTLOADER_OFFSET}. These are addresses used by the ROM bootlo…
86 …The ESP8266 SDK stores WiFi configuration at the "end" of flash, and it finds the end using this s…
88 …ules (and boards that use them such as NodeMCU, HUZZAH, etc.) usually have at least 4 megabyte / `…
120 …The ESP-IDF flashes a partition table to the flash at offset 0x8000. All of the partitions in this…
/hal_espressif-latest/components/esp_system/ld/esp32c2/
Dsections.ld.in39 * This section MUST be placed at the beginning of the DRAM0,
75 * This section holds data that should not be initialized at power up.
150 * Thus, it must have its alignment and (at least) its size.
155 /* Start at the same alignment constraint than .flash.text */
246 /* Keep this section shall be at least aligned on 4 */
267 This section is a place where we dump all the rodata which aren't used at runtime,
313 * This section needs to be placed at the end of the IRAM0,
/hal_espressif-latest/components/esp_hw_support/port/esp32h2/
DKconfig.rtc13 bool "External 32kHz oscillator at 32K_XP pin"
31 When this option is set to 0, clock calibration will not be performed at
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
DKconfig.rtc13 bool "External 32kHz oscillator at 32K_XP pin"
33 When this option is set to 0, clock calibration will not be performed at
/hal_espressif-latest/components/esp_hw_support/port/esp32c2/
DKconfig.rtc10 bool "External 32kHz oscillator at pin0"
29 When this option is set to 0, clock calibration will not be performed at
/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
DKconfig.rtc13 bool "External 32kHz oscillator at 32K_XP pin"
33 When this option is set to 0, clock calibration will not be performed at
/hal_espressif-latest/components/esp_hw_support/port/esp32s2/
DKconfig.rtc11 - "External 32kHz crystal" provides better frequency stability, at the
28 bool "External 32kHz oscillator at 32K_XN pin"
48 When this option is set to 0, clock calibration will not be performed at

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