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Searched refs:_SPI_CACHE_PORT (Results 1 – 2 of 2) sorted by relevance

/hal_espressif-latest/components/esp_psram/esp32s2/
Desp_psram_impl_quad.c92 #define _SPI_CACHE_PORT 0 macro
354 …SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 1, SP… in psram_set_spi0_cache_cs_timing()
355 …SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, S… in psram_set_spi0_cache_cs_timing()
356 …SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_S… in psram_set_spi0_cache_cs_timing()
358 …SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_T… in psram_set_spi0_cache_cs_timing()
359 …SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP… in psram_set_spi0_cache_cs_timing()
360 … SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in psram_set_spi0_cache_cs_timing()
362 CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_CS_HOLD_M | SPI_CS_SETUP_M); in psram_set_spi0_cache_cs_timing()
404 if (spi_num == _SPI_CACHE_PORT) { in psram_set_clk_mode()
468 psram_set_clk_mode(_SPI_CACHE_PORT, clk_mode); in esp_psram_impl_enable()
/hal_espressif-latest/components/esp_psram/esp32/
Desp_psram_impl_quad.c167 #define _SPI_CACHE_PORT 0 macro
733 g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M; in psram_gpio_config()
735 …SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRA… in psram_gpio_config()
736 esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT); in psram_gpio_config()
744 g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M; in psram_gpio_config()
746 …SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRA… in psram_gpio_config()
747 esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT); in psram_gpio_config()
755 g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_40M; in psram_gpio_config()
757 …SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRA… in psram_gpio_config()
758 esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_CACHE_PORT); in psram_gpio_config()
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