Home
last modified time | relevance | path

Searched refs:SOC_CPU_CORES_NUM (Results 1 – 25 of 43) sorted by relevance

12

/hal_espressif-latest/components/esp_hw_support/
Dcpu.c46 assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM); in esp_cpu_stall()
47 #if SOC_CPU_CORES_NUM > 1 // We don't allow stalling of the current core in esp_cpu_stall()
70 assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM); in esp_cpu_unstall()
71 #if SOC_CPU_CORES_NUM > 1 // We don't allow stalling of the current core in esp_cpu_unstall()
93 assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM); in esp_cpu_reset()
94 #if SOC_CPU_CORES_NUM > 1 in esp_cpu_reset()
Dintr_alloc.c99 static uint32_t non_iram_int_mask[SOC_CPU_CORES_NUM];
102 static uint32_t non_iram_int_disabled[SOC_CPU_CORES_NUM];
103 static bool non_iram_int_disabled_flag[SOC_CPU_CORES_NUM];
198 if (cpu >= SOC_CPU_CORES_NUM) { in esp_intr_mark_shared()
222 if (cpu >= SOC_CPU_CORES_NUM) { in esp_intr_reserve()
/hal_espressif-latest/components/esp_system/
Dstartup.c88 #if !(SOC_CPU_CORES_NUM > 1) && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
125 static volatile bool s_system_inited[SOC_CPU_CORES_NUM] = { false };
127 const sys_startup_fn_t g_startup_fn[SOC_CPU_CORES_NUM] = { [0] = start_cpu0,
128 #if SOC_CPU_CORES_NUM > 1
129 [1 ... SOC_CPU_CORES_NUM - 1] = start_cpu_other_cores
440 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) { in do_secondary_init()
503 #if SOC_CPU_CORES_NUM > 1 && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE in start_cpu0_default()
Dsystick_etm.c30 …ESP_GOTO_ON_FALSE(out_event && core_id < SOC_CPU_CORES_NUM, ESP_ERR_INVALID_ARG, err, TAG, "invali… in esp_systick_new_etm_alarm_event()
/hal_espressif-latest/components/esp_rom/patches/
Desp_rom_sys.c46 #if SOC_CPU_CORES_NUM > 1
55 #if SOC_CPU_CORES_NUM > 1 in esp_rom_set_cpu_ticks_per_us()
Desp_rom_wdt.c57 #if SOC_CPU_CORES_NUM > 1 in wdt_hal_init()
/hal_espressif-latest/components/esp_system/include/esp_private/
Dstartup_internal.h29 extern sys_startup_fn_t const g_startup_fn[SOC_CPU_CORES_NUM];
77 #define ESP_SYSTEM_INIT_ALL_CORES (BIT(SOC_CPU_CORES_NUM) - 1)
Dpanic_internal.h24 extern void *g_exc_frames[SOC_CPU_CORES_NUM];
/hal_espressif-latest/components/esp_system/port/
Dcpu_start.c138 static volatile bool s_cpu_up[SOC_CPU_CORES_NUM] = { false };
139 static volatile bool s_cpu_inited[SOC_CPU_CORES_NUM] = { false };
256 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) { in start_other_core()
297 for (unsigned core = 1; core < SOC_CPU_CORES_NUM; core++) { in do_multicore_settings()
315 soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM];
515 #if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors
722 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
Dpanic_handler.c48 void *g_exc_frames[SOC_CPU_CORES_NUM] = {NULL};
91 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
156 for (uint32_t i = 0; i < SOC_CPU_CORES_NUM; i++) {
Desp_system_chip.c49 for (uint32_t i = 0; i < SOC_CPU_CORES_NUM; i++) { in esp_restart_noos_dig()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Desp_cpu_intr.c19 uint32_t flags[SOC_CPU_CORES_NUM];
71 assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM && intr_desc_ret != NULL); in esp_cpu_intr_get_desc()
/hal_espressif-latest/components/esp_hw_support/include/hal/
Dsoc_hal.h20 #if SOC_CPU_CORES_NUM > 1 // We only allow stalling/unstalling of other cores
Dinterrupt_controller_hal.h38 int_desc_flag_t cpuflags[SOC_CPU_CORES_NUM];
/hal_espressif-latest/components/soc/include/soc/
Ddedic_gpio_periph.h33 } cores[SOC_CPU_CORES_NUM]; // Signals routed to/from GPIO matrix
/hal_espressif-latest/components/esp_hw_support/port/esp32/
Desp_cpu_intr.c21 uint32_t flags[SOC_CPU_CORES_NUM];
203 assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM && intr_desc_ret != NULL); in esp_cpu_intr_get_desc()
/hal_espressif-latest/components/newlib/
Dabort.c20 _Static_assert(SOC_CPU_CORES_NUM < 10, "abort() assumes number of cores is 1 to 9"); in abort()
/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_init.c121 #if (SOC_CPU_CORES_NUM > 1) in bootloader_print_banner()
/hal_espressif-latest/zephyr/common/
Dsoc_init.c38 #if (SOC_CPU_CORES_NUM > 1) in print_banner()
/hal_espressif-latest/components/esp_system/port/soc/esp32s3/
Dhighint_hdl.S33 ….space L4_INTR_STACK_SIZE*SOC_CPU_CORES_NUM /* This allocates stacks for each individual CPU.…
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dsoc_caps.h91 #define SOC_CPU_CORES_NUM (1U) macro
/hal_espressif-latest/components/riscv/include/riscv/
Drv_utils.h42 #if SOC_CPU_CORES_NUM == 1 in rv_utils_get_core_id()
/hal_espressif-latest/components/esp_timer/src/
Desp_timer_impl_systimer.c141 for (unsigned cpuid = 0; cpuid < SOC_CPU_CORES_NUM; ++cpuid) { in esp_timer_impl_early_init()
/hal_espressif-latest/components/xtensa/include/
Dxt_utils.h33 #if SOC_CPU_CORES_NUM > 1 in xt_utils_get_core_id()
/hal_espressif-latest/components/soc/esp32/include/soc/
Dsoc_caps.h145 #define SOC_CPU_CORES_NUM 2 macro

12