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Searched refs:RTC_CNTL_TIMER1_REG (Results 1 – 20 of 20) sorted by relevance

/hal_espressif-latest/components/esp_hw_support/port/esp32/
Drtc_init.c36 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait); in rtc_init()
37 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, cfg.xtal_wait); in rtc_init()
38 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait); in rtc_init()
Drtc_sleep.c241 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); in rtc_sleep_low_init()
242 …REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_… in rtc_sleep_low_init()
243 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES); in rtc_sleep_low_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32c2/
Drtc_sleep.c199 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); in rtc_sleep_low_init()
200 …REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_… in rtc_sleep_low_init()
201 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES); in rtc_sleep_low_init()
Drtc_init.c37 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait); in rtc_init()
38 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait); in rtc_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
Drtc_sleep.c250 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); in rtc_sleep_low_init()
251 …REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_… in rtc_sleep_low_init()
252 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES); in rtc_sleep_low_init()
Drtc_init.c49 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait); in rtc_init()
50 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait); in rtc_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Drtc_sleep.c262 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); in rtc_sleep_low_init()
263 …REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_… in rtc_sleep_low_init()
264 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES); in rtc_sleep_low_init()
Drtc_init.c62 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait); in rtc_init()
63 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait); in rtc_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32s2/
Drtc_sleep.c255 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); in rtc_sleep_low_init()
256 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES); in rtc_sleep_low_init()
257 …REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_… in rtc_sleep_low_init()
Drtc_init.c43 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait); in rtc_init()
44 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait); in rtc_init()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dclk_tree_ll.h69 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT); in clk_ll_rc_fast_enable()
78 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT); in clk_ll_rc_fast_disable()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dclk_tree_ll.h138 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT); in clk_ll_rc_fast_enable()
147 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT); in clk_ll_rc_fast_disable()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dclk_tree_ll.h136 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT); in clk_ll_rc_fast_enable()
145 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT); in clk_ll_rc_fast_disable()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dclk_tree_ll.h222 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT); in clk_ll_rc_fast_enable()
231 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT); in clk_ll_rc_fast_disable()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dclk_tree_ll.h270 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT); in clk_ll_rc_fast_enable()
279 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT); in clk_ll_rc_fast_disable()
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Drtc_cntl_reg.h245 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1C) macro
/hal_espressif-latest/components/soc/esp32/include/soc/
Drtc_cntl_reg.h315 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drtc_cntl_reg.h282 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Drtc_cntl_reg.h273 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) macro
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Drtc_cntl_reg.h266 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1C) macro