Searched refs:RTC_CNTL_FIB_SEL_REG (Results 1 – 9 of 9) sorted by relevance
| /hal_espressif-latest/components/bootloader_support/src/esp32c3/ |
| D | bootloader_soc.c | 12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config()
23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in bootloader_ana_bod_reset_config()
34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()
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| /hal_espressif-latest/components/bootloader_support/src/esp32s3/ |
| D | bootloader_soc.c | 12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config()
23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in bootloader_ana_bod_reset_config()
34 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in bootloader_ana_clock_glitch_reset_config()
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| /hal_espressif-latest/zephyr/esp32c3/src/ |
| D | soc_init.c | 31 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in ana_super_wdt_reset_config()
42 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in ana_bod_reset_config()
53 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in ana_clock_glitch_reset_config()
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| /hal_espressif-latest/components/bootloader_support/src/esp32c2/ |
| D | bootloader_soc.c | 12 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in bootloader_ana_super_wdt_reset_config()
23 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in bootloader_ana_bod_reset_config()
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| /hal_espressif-latest/zephyr/esp32s3/src/ |
| D | soc_init.c | 20 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in ana_super_wdt_reset_config()
31 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in ana_bod_reset_config()
42 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_GLITCH_RST); in ana_clock_glitch_reset_config()
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| /hal_espressif-latest/zephyr/esp32c2/src/ |
| D | soc_init.c | 21 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); in ana_super_wdt_reset_config()
32 REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST); in ana_bod_reset_config()
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | rtc_cntl_reg.h | 1673 #define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0xF8) macro
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | rtc_cntl_reg.h | 2347 #define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x010C) macro
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | rtc_cntl_reg.h | 3565 #define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x148) macro
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