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Searched refs:RTC_CNTL_CLK_CONF_REG (Results 1 – 25 of 32) sorted by relevance

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/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dclk_tree_ll.h68 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); in clk_ll_rc_fast_enable()
77 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); in clk_ll_rc_fast_disable()
88 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in clk_ll_rc_fast_is_enabled()
101 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); in clk_ll_rc_fast_d256_enable()
112 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); in clk_ll_rc_fast_d256_disable()
122 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in clk_ll_rc_fast_d256_is_enabled()
130 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_enable()
138 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_disable()
148 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_is_enabled()
156 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); in clk_ll_rc_fast_d256_digi_enable()
[all …]
Drtc_cntl_ll.h44 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in rtc_cntl_ll_enable_cpu_retention()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dclk_tree_ll.h137 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); in clk_ll_rc_fast_enable()
146 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); in clk_ll_rc_fast_disable()
157 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in clk_ll_rc_fast_is_enabled()
170 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); in clk_ll_rc_fast_d256_enable()
181 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); in clk_ll_rc_fast_d256_disable()
191 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in clk_ll_rc_fast_d256_is_enabled()
199 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_enable()
207 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_disable()
217 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_is_enabled()
225 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); in clk_ll_rc_fast_d256_digi_enable()
[all …]
Drtc_cntl_ll.h118 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); /* Enable internal 20 MHz clock */ in rtc_cntl_ll_enable_cpu_retention_clock()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dclk_tree_ll.h135 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); in clk_ll_rc_fast_enable()
144 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); in clk_ll_rc_fast_disable()
155 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in clk_ll_rc_fast_is_enabled()
168 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); in clk_ll_rc_fast_d256_enable()
179 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); in clk_ll_rc_fast_d256_disable()
189 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in clk_ll_rc_fast_d256_is_enabled()
197 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_enable()
205 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_disable()
215 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_is_enabled()
223 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); in clk_ll_rc_fast_d256_digi_enable()
[all …]
Drtc_cntl_ll.h46 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in rtc_cntl_ll_enable_cpu_retention_clock()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dclk_tree_ll.h269 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); in clk_ll_rc_fast_enable()
278 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); in clk_ll_rc_fast_disable()
289 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in clk_ll_rc_fast_is_enabled()
302 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); in clk_ll_rc_fast_d256_enable()
313 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); in clk_ll_rc_fast_d256_disable()
323 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in clk_ll_rc_fast_d256_is_enabled()
331 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_enable()
339 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_disable()
349 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_is_enabled()
357 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); in clk_ll_rc_fast_d256_digi_enable()
[all …]
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dclk_tree_ll.h221 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); in clk_ll_rc_fast_enable()
230 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); in clk_ll_rc_fast_disable()
241 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in clk_ll_rc_fast_is_enabled()
254 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); in clk_ll_rc_fast_d256_enable()
265 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); in clk_ll_rc_fast_d256_disable()
275 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in clk_ll_rc_fast_d256_is_enabled()
283 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_enable()
291 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_disable()
301 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_is_enabled()
309 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN_M); in clk_ll_rc_fast_d256_digi_enable()
[all …]
/hal_espressif-latest/components/esp_hw_support/port/esp32c2/
Drtc_sleep.c178 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
179 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING); in rtc_sleep_init()
181 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
182 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING); in rtc_sleep_init()
193 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu); in rtc_sleep_init()
Drtc_clk_init.c38 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
Drtc_init.c75 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
Drtc_sleep.c229 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
230 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING); in rtc_sleep_init()
232 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
233 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING); in rtc_sleep_init()
244 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu); in rtc_sleep_init()
Drtc_clk_init.c38 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Drtc_sleep.c241 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
243 REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
256 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu); in rtc_sleep_init()
Drtc_clk_init.c35 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
/hal_espressif-latest/components/esp_hw_support/port/esp32s2/
Drtc_clk_init.c37 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
Drtc_sleep.c236 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
238 REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
Drtc_init.c93 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_init()
/hal_espressif-latest/zephyr/esp32s2/src/
Dsoc_random.c31 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in soc_random_enable()
/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random_esp32s2.c36 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in bootloader_random_enable()
Dbootloader_random_esp32s3.c23 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in bootloader_random_enable()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_random.c24 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); in soc_random_enable()
/hal_espressif-latest/components/esp_hw_support/port/esp32/
Drtc_clk_init.c62 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); in rtc_clk_init()
Drtc_sleep.c219 REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
221 REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_sleep_init()
Drtc_init.c65 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); in rtc_init()

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