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Searched refs:REG_READ (Results 1 – 25 of 120) sorted by relevance

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/hal_espressif-latest/components/bootloader_support/src/esp32s3/
Dbootloader_esp32s3.c66 inst = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG); in wdt_reset_info_dump()
67 dstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG); in wdt_reset_info_dump()
68 data = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG); in wdt_reset_info_dump()
69 pc = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG); in wdt_reset_info_dump()
70 lsstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG); in wdt_reset_info_dump()
71 lsaddr = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG); in wdt_reset_info_dump()
72 lsdata = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG); in wdt_reset_info_dump()
75 inst = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG); in wdt_reset_info_dump()
76 dstat = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG); in wdt_reset_info_dump()
77 data = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG); in wdt_reset_info_dump()
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/hal_espressif-latest/components/esp_system/port/arch/xtensa/
Dpanic_arch.c176 status[0] = REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG); in print_cache_err_details()
177 status[1] = REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG); in print_cache_err_details()
181 vaddr = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC0_REG); in print_cache_err_details()
182 size = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC1_REG); in print_cache_err_details()
190 vaddr = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG); in print_cache_err_details()
191 size = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG); in print_cache_err_details()
199 vaddr = REG_READ(EXTMEM_PRO_ICACHE_REJECT_VADDR_REG); in print_cache_err_details()
203 if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) { in print_cache_err_details()
213 vaddr = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC0_REG); in print_cache_err_details()
214 size = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC1_REG); in print_cache_err_details()
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/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dmemprot_ll.h27 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1; in memprot_ll_get_iram0_dram0_split_line_lock()
119 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG) & 0x3F; in memprot_ll_get_iram0_split_line_main_I_D_cat()
124 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG) & 0x3F; in memprot_ll_get_iram0_split_line_I_0_cat()
129 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG) & 0x3F; in memprot_ll_get_iram0_split_line_I_1_cat()
134 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_main_I_D()
139 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_I_0()
144 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_I_1()
158 return REG_READ(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG) == 1; in memprot_ll_iram0_get_pms_lock()
241 return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1; in memprot_ll_iram0_get_monitor_lock()
276 return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG); in memprot_ll_iram0_get_monitor_enable_register()
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Dhmac_ll.h103 return REG_READ(HMAC_QUERY_ERROR_REG); in hmac_ll_config_error()
113 query = REG_READ(HMAC_QUERY_BUSY_REG); in hmac_ll_wait_idle()
137 result[i] = REG_READ(HMAC_RDATA_BASE + (i * REG_WIDTH)); in hmac_ll_read_result_256()
Dds_ll.h43 return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false; in ds_ll_busy()
59 uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG); in ds_ll_key_error_source()
137 uint32_t result = REG_READ(DS_QUERY_CHECK_REG); in ds_ll_check_signature()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dmemprot_ll.h47 …HAL_ASSERT((REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1) && "Value … in memprot_ll_set_iram0_dram0_split_line_lock()
53 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1; in memprot_ll_get_iram0_dram0_split_line_lock()
163 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG); in memprot_ll_get_iram0_split_line_main_I_D_regval()
168 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG); in memprot_ll_get_iram0_split_line_main_I_0_regval()
173 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG); in memprot_ll_get_iram0_split_line_main_I_1_regval()
222 HAL_ASSERT((REG_READ(sensitive_reg) == regval) && "Value not stored to required register"); in memprot_ll_set_iram0_split_line()
248 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG) & 0x3FFF; in memprot_ll_get_iram0_split_line_main_I_D_cat()
253 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG) & 0x3FFF; in memprot_ll_get_iram0_split_line_I_0_cat()
258 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG) & 0x3FFF; in memprot_ll_get_iram0_split_line_I_1_cat()
264 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_main_I_D()
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Dhmac_ll.h92 return REG_READ(HMAC_QUERY_ERROR_REG); in hmac_ll_config_error()
102 query = REG_READ(HMAC_QUERY_BUSY_REG); in hmac_ll_wait_idle()
126 result[i] = REG_READ(HMAC_RDATA_BASE + (i * REG_WIDTH)); in hmac_ll_read_result_256()
Dds_ll.h30 return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false; in ds_ll_busy()
46 uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG); in ds_ll_key_error_source()
125 uint32_t result = REG_READ(DS_QUERY_CHECK_REG); in ds_ll_check_signature()
Daes_ll.h92 output_word = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH)); in aes_ll_read_block()
115 return REG_READ(AES_STATE_REG); in aes_ll_get_state()
187 iv_word = REG_READ(AES_IV_BASE + (i * REG_WIDTH)); in aes_ll_read_iv()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_init.c75 inst = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG); in wdt_reset_info_dump()
76 dstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG); in wdt_reset_info_dump()
77 data = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG); in wdt_reset_info_dump()
78 pc = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG); in wdt_reset_info_dump()
79 lsstat = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG); in wdt_reset_info_dump()
80 lsaddr = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG); in wdt_reset_info_dump()
81 lsdata = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG); in wdt_reset_info_dump()
/hal_espressif-latest/components/bootloader_support/src/esp32s2/
Dbootloader_esp32s2.c65 inst = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGINST); in wdt_reset_info_dump()
66 dstat = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS); in wdt_reset_info_dump()
67 data = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGDATA); in wdt_reset_info_dump()
68 pc = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGPC); in wdt_reset_info_dump()
69 lsstat = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT); in wdt_reset_info_dump()
70 lsaddr = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR); in wdt_reset_info_dump()
71 lsdata = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA); in wdt_reset_info_dump()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dmemprot_ll.h44 return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1; in memprot_ll_get_iram0_dram0_split_line_lock()
136 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_main_I_D()
141 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_I_0()
146 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_iram0_split_line_I_1()
162 return REG_READ(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG) == 1; in memprot_ll_iram0_get_pms_lock()
246 return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1; in memprot_ll_iram0_get_monitor_lock()
276 return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG); in memprot_ll_iram0_get_monitor_enable_register()
308 return REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG); in memprot_ll_iram0_get_monitor_status_register()
387 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_dram0_split_line_D_0()
392 …return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CON… in memprot_ll_get_dram0_split_line_D_1()
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/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random.c47 random = REG_READ(WDEV_RND_REG); in bootloader_fill_random()
50 random ^= REG_READ(WDEV_RND_REG); in bootloader_fill_random()
69 random = REG_READ(WDEV_RND_REG); in bootloader_fill_random()
72 random ^= REG_READ(WDEV_RND_REG); in bootloader_fill_random()
/hal_espressif-latest/components/hal/esp32c3/
Defuse_hal.c80 if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) { in efuse_hal_is_coding_error_in_block()
93 uint32_t err_fail_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4); in efuse_hal_is_coding_error_in_block()
94 uint32_t err_num_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + ((block - 1) / 8) * 4); in efuse_hal_is_coding_error_in_block()
/hal_espressif-latest/components/riscv/
Dinterrupt.c72 return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG); in esprv_intc_get_interrupt_unmask()
79 uint32_t intr_type_reg = REG_READ(INTERRUPT_CORE0_CPU_INT_TYPE_REG); in esprv_intc_int_get_type()
85 uint32_t intr_priority_reg = REG_READ(INTC_INT_PRIO_REG(rv_int_num)); in esprv_intc_int_get_priority()
/hal_espressif-latest/components/esp_hw_support/
Dhw_random.c66 result ^= REG_READ(WDEV_RND_REG); in esp_random()
74 result ^= REG_READ(WDEV_RND_REG); in esp_random()
78 return result ^ REG_READ(WDEV_RND_REG); in esp_random()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Daes_ll.h93 output_word = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH)); in aes_ll_read_block()
126 return REG_READ(AES_STATE_REG); in aes_ll_get_state()
198 iv_word = REG_READ(AES_IV_BASE + (i * REG_WIDTH)); in aes_ll_read_iv()
244 hash_word = REG_READ(AES_H_BASE + (i * REG_WIDTH)); in aes_ll_gcm_read_hash()
304 tag_word = REG_READ(AES_T_BASE + (i * REG_WIDTH)); in aes_ll_gcm_read_tag()
/hal_espressif-latest/components/esp_timer/src/
Desp_timer_impl_lac.c114 uint32_t lo_start = REG_READ(COUNT_LO_REG); in esp_timer_impl_get_counter_reg()
121 lo = REG_READ(COUNT_LO_REG); in esp_timer_impl_get_counter_reg()
131 hi = REG_READ(COUNT_HI_REG); in esp_timer_impl_get_counter_reg()
132 lo = REG_READ(COUNT_LO_REG); in esp_timer_impl_get_counter_reg()
273 .lo = REG_READ(ALARM_LO_REG), in esp_timer_impl_get_alarm_reg()
274 .hi = REG_READ(ALARM_HI_REG) in esp_timer_impl_get_alarm_reg()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dhmac_ll.h95 return REG_READ(HMAC_QUERY_ERROR_REG); in hmac_ll_config_error()
105 query = REG_READ(HMAC_QUERY_BUSY_REG); in hmac_ll_wait_idle()
129 result[i] = REG_READ(HMAC_RD_RESULT_MEM + (i * REG_WIDTH)); in hmac_ll_read_result_256()
Dds_ll.h35 return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false; in ds_ll_busy()
51 uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG); in ds_ll_key_error_source()
129 uint32_t result = REG_READ(DS_QUERY_CHECK_REG); in ds_ll_check_signature()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dhmac_ll.h95 return REG_READ(HMAC_QUERY_ERROR_REG); in hmac_ll_config_error()
105 query = REG_READ(HMAC_QUERY_BUSY_REG); in hmac_ll_wait_idle()
129 result[i] = REG_READ(HMAC_RD_RESULT_MEM + (i * REG_WIDTH)); in hmac_ll_read_result_256()
Dds_ll.h35 return (REG_READ(DS_QUERY_BUSY_REG) > 0) ? true : false; in ds_ll_busy()
51 uint32_t key_error = REG_READ(DS_QUERY_KEY_WRONG_REG); in ds_ll_key_error_source()
129 uint32_t result = REG_READ(DS_QUERY_CHECK_REG); in ds_ll_check_signature()
Daes_ll.h92 output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH)); in aes_ll_read_block()
115 return REG_READ(AES_STATE_REG); in aes_ll_get_state()
187 iv_word = REG_READ(AES_IV_MEM + (i * REG_WIDTH)); in aes_ll_read_iv()
/hal_espressif-latest/components/esp_system/port/soc/esp32s2/
Dcache_err_int.c72 if (REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG) != 0 || in esp_cache_err_get_cpuid()
73 REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG) != 0) { in esp_cache_err_get_cpuid()
/hal_espressif-latest/components/efuse/esp32c3/
Desp_efuse_utility.c75 uint32_t error_reg = REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4); in esp_efuse_utility_check_errors()
77 uint32_t data_reg = REG_READ(EFUSE_RD_REPEAT_DATA0_REG + i * 4); in esp_efuse_utility_check_errors()
100 virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); in esp_efuse_utility_burn_chip()
115 if (REG_READ(addr_wr_block) != 0) { in esp_efuse_utility_burn_chip()
202 if (REG_READ(addr_wr_block)) { in esp_efuse_utility_apply_new_coding_scheme()

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