1 /*
2 * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7
8 #include <stdint.h>
9 #include <stddef.h>
10 #include <string.h>
11 #include <sys/param.h>
12 #include "esp_attr.h"
13 #include "esp_cpu.h"
14 #include "soc/wdev_reg.h"
15 #include "esp_private/esp_clk.h"
16
17 #if SOC_LP_TIMER_SUPPORTED
18 #include "hal/lp_timer_hal.h"
19 #endif
20
21 #if defined CONFIG_IDF_TARGET_ESP32S3
22 #define APB_CYCLE_WAIT_NUM (1778) /* If APB clock is 80 MHz, the maximum sampling frequency is around 45 KHz*/
23 /* 45 KHz reading frequency is the maximum we have tested so far on S3 */
24 #elif defined CONFIG_IDF_TARGET_ESP32C6
25 #define APB_CYCLE_WAIT_NUM (160 * 16) /* On ESP32C6, we only read one byte at a time, then XOR the value with
26 * an asynchronous timer (see code below).
27 * The current value translates to a sampling frequency of around 62.5 KHz
28 * for reading 8 bit samples, which is the rate at which the RNG was tested,
29 * plus additional overhead for the calculation, making it slower. */
30 #elif defined CONFIG_IDF_TARGET_ESP32H2
31 #define APB_CYCLE_WAIT_NUM (96 * 16) /* Same reasoning as for ESP32C6, but the CPU frequency on ESP32H2 is
32 * 96MHz instead of 160 MHz */
33 #else
34 #define APB_CYCLE_WAIT_NUM (16)
35 #endif
36
esp_random(void)37 uint32_t IRAM_ATTR esp_random(void)
38 {
39 /* The PRNG which implements WDEV_RANDOM register gets 2 bits
40 * of extra entropy from a hardware randomness source every APB clock cycle
41 * (provided WiFi or BT are enabled). To make sure entropy is not drained
42 * faster than it is added, this function needs to wait for at least 16 APB
43 * clock cycles after reading previous word. This implementation may actually
44 * wait a bit longer due to extra time spent in arithmetic and branch statements.
45 *
46 * As a (probably unncessary) precaution to avoid returning the
47 * RNG state as-is, the result is XORed with additional
48 * WDEV_RND_REG reads while waiting.
49 */
50
51 /* This code does not run in a critical section, so CPU frequency switch may
52 * happens while this code runs (this will not happen in the current
53 * implementation, but possible in the future). However if that happens,
54 * the number of cycles spent on frequency switching will certainly be more
55 * than the number of cycles we need to wait here.
56 */
57 uint32_t cpu_to_apb_freq_ratio = esp_clk_cpu_freq() / esp_clk_apb_freq();
58
59 static uint32_t last_ccount = 0;
60 uint32_t ccount;
61 uint32_t result = 0;
62 #if SOC_LP_TIMER_SUPPORTED
63 for (size_t i = 0; i < sizeof(result); i++) {
64 do {
65 ccount = esp_cpu_get_cycle_count();
66 result ^= REG_READ(WDEV_RND_REG);
67 } while (ccount - last_ccount < cpu_to_apb_freq_ratio * APB_CYCLE_WAIT_NUM);
68 uint32_t current_rtc_timer_counter = (lp_timer_hal_get_cycle_count() & 0xFF);
69 result ^= ((result ^ current_rtc_timer_counter) & 0xFF) << (i * 8);
70 }
71 #else
72 do {
73 ccount = esp_cpu_get_cycle_count();
74 result ^= REG_READ(WDEV_RND_REG);
75 } while (ccount - last_ccount < cpu_to_apb_freq_ratio * APB_CYCLE_WAIT_NUM);
76 #endif
77 last_ccount = ccount;
78 return result ^ REG_READ(WDEV_RND_REG);
79 }
80
esp_fill_random(void * buf,size_t len)81 void esp_fill_random(void *buf, size_t len)
82 {
83 assert(buf != NULL);
84 uint8_t *buf_bytes = (uint8_t *)buf;
85 while (len > 0) {
86 uint32_t word = esp_random();
87 uint32_t to_copy = MIN(sizeof(word), len);
88 memcpy(buf_bytes, &word, to_copy);
89 buf_bytes += to_copy;
90 len -= to_copy;
91 }
92 }
93
