1 /*
2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "sdkconfig.h"
8 #include <sys/param.h>
9 #include "soc/soc_caps.h"
10 #include "hal/assert.h"
11 #include "hal/efuse_hal.h"
12 #include "hal/efuse_ll.h"
13 #include "esp_attr.h"
14
15 #define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block))))
16 #define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block))))
17
efuse_hal_get_major_chip_version(void)18 IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
19 {
20 return efuse_ll_get_chip_wafer_version_major();
21 }
22
efuse_hal_get_minor_chip_version(void)23 IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
24 {
25 return efuse_ll_get_chip_wafer_version_minor();
26 }
27
28 /******************* eFuse control functions *************************/
29
efuse_hal_set_timing(uint32_t apb_freq_hz)30 void efuse_hal_set_timing(uint32_t apb_freq_hz)
31 {
32 (void) apb_freq_hz;
33 efuse_ll_set_dac_num(0xFF);
34 efuse_ll_set_dac_clk_div(0x28);
35 efuse_ll_set_pwr_on_num(0x3000);
36 efuse_ll_set_pwr_off_num(0x190);
37 }
38
efuse_hal_read(void)39 void efuse_hal_read(void)
40 {
41 efuse_hal_set_timing(0);
42
43 efuse_ll_set_conf_read_op_code();
44 efuse_ll_set_read_cmd();
45
46 while (efuse_ll_get_read_cmd() != 0) { }
47 /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
48 while (efuse_ll_get_read_cmd() != 0) { }
49 }
50
efuse_hal_clear_program_registers(void)51 void efuse_hal_clear_program_registers(void)
52 {
53 ets_efuse_clear_program_registers();
54 }
55
efuse_hal_program(uint32_t block)56 void efuse_hal_program(uint32_t block)
57 {
58 efuse_hal_set_timing(0);
59
60 efuse_ll_set_conf_write_op_code();
61 efuse_ll_set_pgm_cmd(block);
62
63 while (efuse_ll_get_pgm_cmd() != 0) { }
64
65 efuse_hal_clear_program_registers();
66 efuse_hal_read();
67 }
68
efuse_hal_rs_calculate(const void * data,void * rs_values)69 void efuse_hal_rs_calculate(const void *data, void *rs_values)
70 {
71 ets_efuse_rs_calculate(data, rs_values);
72 }
73
74 /******************* eFuse control functions *************************/
75
efuse_hal_is_coding_error_in_block(unsigned block)76 bool efuse_hal_is_coding_error_in_block(unsigned block)
77 {
78 if (block == 0) {
79 for (unsigned i = 0; i < 5; i++) {
80 if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) {
81 return true;
82 }
83 }
84 } else if (block <= 10) {
85 // The order of error in these regs is different only for the C3 chip.
86 // Fail bit (mask=0x8):
87 // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1, ------ (low)
88 // EFUSE_RD_RS_ERR1_REG: BLOCK9, BLOCK8
89 // Error num bits (mask=0x7):
90 // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
91 // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
92 // BLOCK10 is not presented in the error regs.
93 uint32_t err_fail_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
94 uint32_t err_num_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + ((block - 1) / 8) * 4);
95 return (ESP_EFUSE_BLOCK_ERROR_BITS(err_fail_reg, block % 8) != 0) || (ESP_EFUSE_BLOCK_ERROR_NUM_BITS(err_num_reg, (block - 1) % 8) != 0);
96 }
97 return false;
98 }
99
