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Searched refs:REG_GET_FIELD (Results 1 – 25 of 63) sorted by relevance

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/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dmemprot_ll.h207 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_0()
213 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_1()
219 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_2()
225 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_3()
261 …return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_… in memprot_ll_iram0_get_monitor_en()
282 …return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_… in memprot_ll_iram0_get_monitor_status_intr()
287 …return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_… in memprot_ll_iram0_get_monitor_status_fault_wr()
292 …return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_… in memprot_ll_iram0_get_monitor_status_fault_loadstore()
297 …return REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_… in memprot_ll_iram0_get_monitor_status_fault_world()
302 …uint32_t addr = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS… in memprot_ll_iram0_get_monitor_status_fault_addr()
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Dclk_tree_ll.h257 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); in clk_ll_xtal32k_digi_is_enabled()
267 uint32_t pll_freq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); in clk_ll_bbpll_get_freq_mhz()
421 uint32_t clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in clk_ll_cpu_get_src()
462 uint32_t cpu_freq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL); in clk_ll_cpu_get_freq_mhz_from_pll()
492 return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; in clk_ll_cpu_get_divider()
525 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in clk_ll_rtc_slow_get_src()
566 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in clk_ll_rtc_fast_get_src()
597 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; in clk_ll_rc_fast_get_divider()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dmemprot_ll.h107 …uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRA… in memprot_ll_icache_set_pms_area_0()
116 …uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRA… in memprot_ll_icache_set_pms_area_1()
130 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_icache_get_pms_area_0()
136 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_icache_get_pms_area_1()
315 …uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRA… in memprot_ll_iram0_set_pms_area_0()
324 …uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRA… in memprot_ll_iram0_set_pms_area_1()
333 …uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRA… in memprot_ll_iram0_set_pms_area_2()
342 …uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRA… in memprot_ll_iram0_set_pms_area_3()
356 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_0()
362 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_1()
[all …]
Drtc_cntl_ll.h39 return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); in rtc_cntl_ll_ext1_get_wakeup_status()
63 return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL); in rtc_cntl_ll_ext1_get_wakeup_pins()
74 uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); in rtc_cntl_ll_enable_tagmem_retention()
97 uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); in rtc_cntl_ll_disable_tagmem_retention()
123 uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); in rtc_cntl_ll_enable_cpu_retention()
186 return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); in rtc_cntl_ll_get_wakeup_cause()
Dclk_tree_ll.h259 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); in clk_ll_xtal32k_digi_is_enabled()
269 uint32_t pll_freq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); in clk_ll_bbpll_get_freq_mhz()
415 uint32_t clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in clk_ll_cpu_get_src()
459 uint32_t cpu_freq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL); in clk_ll_cpu_get_freq_mhz_from_pll()
493 return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; in clk_ll_cpu_get_divider()
526 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in clk_ll_rtc_slow_get_src()
568 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in clk_ll_rtc_fast_get_src()
599 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; in clk_ll_rc_fast_get_divider()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dmemprot_ll.h211 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_0()
217 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_1()
223 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_2()
229 …uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_… in memprot_ll_iram0_get_pms_area_3()
261 …return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR… in memprot_ll_iram0_get_monitor_en()
282 …return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR… in memprot_ll_iram0_get_monitor_status_intr()
287 …return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR… in memprot_ll_iram0_get_monitor_status_fault_wr()
292 …return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR… in memprot_ll_iram0_get_monitor_status_fault_loadstore()
297 …return REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR… in memprot_ll_iram0_get_monitor_status_fault_world()
302 …uint32_t addr = REG_GET_FIELD( SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PM… in memprot_ll_iram0_get_monitor_status_fault_addr()
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Decc_ll.h106 return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW); in ecc_ll_is_calc_finished()
111 return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE); in ecc_ll_get_mode()
116 return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT); in ecc_ll_get_verification_result()
121 return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); in ecc_ll_get_curve()
Dclk_tree_ll.h190 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); in clk_ll_xtal32k_digi_is_enabled()
201 uint32_t pll_freq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); in clk_ll_bbpll_get_freq_mhz()
313 uint32_t clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); in clk_ll_cpu_get_src()
354 uint32_t cpu_freq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL); in clk_ll_cpu_get_freq_mhz_from_pll()
384 return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT) + 1; in clk_ll_cpu_get_divider()
417 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in clk_ll_rtc_slow_get_src()
458 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in clk_ll_rtc_fast_get_src()
489 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; in clk_ll_rc_fast_get_divider()
/hal_espressif-latest/zephyr/esp32/src/esp_adc_cal/
Desp_adc_cal.c102 return (REG_GET_FIELD(VREF_REG, EFUSE_RD_ADC_VREF) != 0) ? true : false; in check_efuse_vref()
108 if (CHECK_BLK3_FLAG && (REG_GET_FIELD(BLK3_RESERVED_REG, EFUSE_RD_BLK3_PART_RESERVE) == 0)) { in check_efuse_tp()
112 if ((REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_LOW) != 0) && in check_efuse_tp()
113 (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_LOW) != 0) && in check_efuse_tp()
114 (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_HIGH) != 0) && in check_efuse_tp()
115 (REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_HIGH) != 0)) { in check_efuse_tp()
143 uint32_t bits = REG_GET_FIELD(VREF_REG, EFUSE_ADC_VREF); in read_efuse_vref()
156 bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_LOW); in read_efuse_tp_low()
159 bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC2_TP_LOW); in read_efuse_tp_low()
173 bits = REG_GET_FIELD(TP_REG, EFUSE_RD_ADC1_TP_HIGH); in read_efuse_tp_high()
[all …]
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Decc_ll.h169 return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW); in ecc_ll_is_calc_finished()
174 return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE); in ecc_ll_get_mode()
179 return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT); in ecc_ll_get_verification_result()
184 return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); in ecc_ll_get_curve()
189 return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE); in ecc_ll_get_mod_base()
Dspi_flash_encrypted_ll.h114 while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) { in spi_flash_encrypt_ll_calculate_wait_idle()
124 while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) { in spi_flash_encrypt_ll_done()
Dapm_ll.h207 …excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEP… in apm_hp_ll_get_m_exception_info()
208 …excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXC… in apm_hp_ll_get_m_exception_info()
209 …excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXC… in apm_hp_ll_get_m_exception_info()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Decc_ll.h117 return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW); in ecc_ll_is_calc_finished()
122 return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE); in ecc_ll_get_mode()
127 return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT); in ecc_ll_get_verification_result()
132 return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); in ecc_ll_get_curve()
Dspi_flash_encrypted_ll.h114 while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) { in spi_flash_encrypt_ll_calculate_wait_idle()
124 while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) { in spi_flash_encrypt_ll_done()
Dapm_ll.h207 …excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEP… in apm_hp_ll_get_m_exception_info()
208 …excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXC… in apm_hp_ll_get_m_exception_info()
209 …excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXC… in apm_hp_ll_get_m_exception_info()
/hal_espressif-latest/components/esp_rom/patches/
Desp_rom_efuse.c17 uint64_t spiconfig1 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_2_REG, EFUSE_SPI_PAD_CONF_1); in esp_rom_efuse_get_opiconfig()
18 uint64_t spiconfig2 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_SPI_PAD_CONF_2); in esp_rom_efuse_get_opiconfig()
Desp_rom_regi2c_esp32s2.c119 return REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA); in esp_rom_regi2c_read()
131 uint32_t data = REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA); in esp_rom_regi2c_read_mask()
157 temp = REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA); in esp_rom_regi2c_write_mask()
Desp_rom_cache_esp32s2_esp32s3.c42 while (REG_GET_FIELD(EXTMEM_CACHE_STATE_REG, EXTMEM_ICACHE_STATE) != 1) { in Cache_Wait_Idle()
46 while (REG_GET_FIELD(EXTMEM_CACHE_STATE_REG, EXTMEM_DCACHE_STATE) != 1) { in Cache_Wait_Idle()
Desp_rom_regi2c_esp32h2.c128 uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); in regi2c_read_impl()
144 uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); in regi2c_read_mask_impl()
177 temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); in regi2c_write_mask_impl()
Desp_rom_hp_regi2c_esp32c6.c129 uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); in regi2c_read_impl()
145 uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); in regi2c_read_mask_impl()
178 temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA); in regi2c_write_mask_impl()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Drtc_cntl_ll.h35 return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); in rtc_cntl_ll_ext1_get_wakeup_status()
59 return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL); in rtc_cntl_ll_ext1_get_wakeup_pins()
105 return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); in rtc_cntl_ll_get_wakeup_cause()
Dclk_tree_ll.h343 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); in clk_ll_xtal32k_digi_is_enabled()
482 uint32_t clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL); in clk_ll_cpu_get_src()
561 return REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT) + 1; in clk_ll_cpu_get_divider()
640 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in clk_ll_rtc_slow_get_src()
681 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in clk_ll_rtc_fast_get_src()
712 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; in clk_ll_rc_fast_get_divider()
/hal_espressif-latest/components/hal/esp32/include/hal/
Drtc_cntl_ll.h33 return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); in rtc_cntl_ll_ext1_get_wakeup_status()
57 return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL); in rtc_cntl_ll_ext1_get_wakeup_pins()
117 return REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE); in rtc_cntl_ll_get_wakeup_cause()
Dclk_tree_ll.h153 return REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); in clk_ll_apll_is_fpd()
391 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN); in clk_ll_xtal32k_digi_is_enabled()
560 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); in clk_ll_cpu_get_src()
637 return REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT) + 1; in clk_ll_cpu_get_divider()
724 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); in clk_ll_rtc_slow_get_src()
765 uint32_t clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL); in clk_ll_rtc_fast_get_src()
794 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL) + 1; in clk_ll_rc_fast_get_divider()
/hal_espressif-latest/components/esp_hw_support/port/esp32s2/
Drtc_time.c76 cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); in rtc_clk_cal_internal_oneoff()
98 in_calibration_clk = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL); in rtc_clk_cal_internal_cycling()
99 uint32_t cali_slowclk_cycles = REG_GET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX); in rtc_clk_cal_internal_cycling()
111 uint32_t cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); in rtc_clk_cal_internal_cycling()

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