1 /**
2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include "esp_rom_sys.h"
7 #include "esp_attr.h"
8 #include "soc/i2c_ana_mst_reg.h"
9 #include "modem/modem_lpcon_reg.h"
10
11 /**
12 * BB - 0x67 - BIT0
13 * TXRF - 0x6B - BIT1
14 * SDM - 0x63 - BIT2
15 * PLL - 0x62 - BIT3
16 * BIAS - 0x6A - BIT4
17 * BBPLL - 0x66 - BIT5
18 * ULP - 0x61 - BIT6
19 * SAR - 0x69 - BIT7
20 * PMU - 0x6d - BIT8
21 */
22
23 #define REGI2C_BIAS_MST_SEL (BIT(8))
24 #define REGI2C_BBPLL_MST_SEL (BIT(9))
25 #define REGI2C_ULP_CAL_MST_SEL (BIT(10))
26 #define REGI2C_SAR_I2C_MST_SEL (BIT(11))
27 #define REGI2C_DIG_REG_MST_SEL (BIT(12))
28
29 #define REGI2C_BIAS_RD_MASK (~BIT(6) & I2C_MST_ANA_CONF1_M)
30 #define REGI2C_BBPLL_RD_MASK (~BIT(7) & I2C_MST_ANA_CONF1_M)
31 #define REGI2C_ULP_CAL_RD_MASK (~BIT(8) & I2C_MST_ANA_CONF1_M)
32 #define REGI2C_SAR_I2C_RD_MASK (~BIT(9) & I2C_MST_ANA_CONF1_M)
33 #define REGI2C_DIG_REG_RD_MASK (~BIT(10) & I2C_MST_ANA_CONF1_M)
34
35 #define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
36
37 #define REGI2C_RTC_BUSY (BIT(25))
38 #define REGI2C_RTC_BUSY_M (BIT(25))
39 #define REGI2C_RTC_BUSY_V 0x1
40 #define REGI2C_RTC_BUSY_S 25
41
42 #define REGI2C_RTC_WR_CNTL (BIT(24))
43 #define REGI2C_RTC_WR_CNTL_M (BIT(24))
44 #define REGI2C_RTC_WR_CNTL_V 0x1
45 #define REGI2C_RTC_WR_CNTL_S 24
46
47 #define REGI2C_RTC_DATA 0x000000FF
48 #define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
49 #define REGI2C_RTC_DATA_V 0xFF
50 #define REGI2C_RTC_DATA_S 16
51
52 #define REGI2C_RTC_ADDR 0x000000FF
53 #define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
54 #define REGI2C_RTC_ADDR_V 0xFF
55 #define REGI2C_RTC_ADDR_S 8
56
57 #define REGI2C_RTC_SLAVE_ID 0x000000FF
58 #define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
59 #define REGI2C_RTC_SLAVE_ID_V 0xFF
60 #define REGI2C_RTC_SLAVE_ID_S 0
61
62 /* SLAVE */
63
64 #define REGI2C_BBPLL (0x66)
65 #define REGI2C_BBPLL_HOSTID 0
66
67 #define REGI2C_BIAS (0x6a)
68 #define REGI2C_BIAS_HOSTID 0
69
70 #define REGI2C_PMU (0x6d)
71 #define REGI2C_PMU_HOSTID 0
72
73 #define REGI2C_ULP_CAL (0x61)
74 #define REGI2C_ULP_CAL_HOSTID 0
75
76 #define REGI2C_SAR_I2C (0x69)
77 #define REGI2C_SAR_I2C_HOSTID 0
78
79 /* SLAVE END */
80
81 uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl")));
82 uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl")));
83 void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl")));
84 void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl")));
85
regi2c_enable_block(uint8_t block)86 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
87 {
88 uint32_t i2c_sel = 0;
89 REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
90
91 /* Before config I2C register, enable corresponding slave. */
92 switch (block) {
93 case REGI2C_BBPLL :
94 i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL);
95 REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK);
96 break;
97 case REGI2C_BIAS :
98 i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL);
99 REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK);
100 break;
101 case REGI2C_PMU:
102 i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL);
103 REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK);
104 break;
105 case REGI2C_ULP_CAL:
106 i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL);
107 REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK);
108 break;
109 case REGI2C_SAR_I2C:
110 i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL);
111 REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK);
112 break;
113 }
114
115 return (uint8_t)(i2c_sel ? 0: 1);
116 }
117
regi2c_read_impl(uint8_t block,uint8_t host_id,uint8_t reg_add)118 uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add)
119 {
120 (void)host_id;
121 uint8_t i2c_sel = regi2c_enable_block(block);
122
123 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
124 uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
125 | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
126 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
127 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
128 uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
129
130 return ret;
131 }
132
regi2c_read_mask_impl(uint8_t block,uint8_t host_id,uint8_t reg_add,uint8_t msb,uint8_t lsb)133 uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
134 {
135 assert(msb - lsb < 8);
136 uint8_t i2c_sel = regi2c_enable_block(block);
137
138 (void)host_id;
139 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
140 uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
141 | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
142 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
143 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
144 uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
145 uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
146
147 return ret;
148 }
149
regi2c_write_impl(uint8_t block,uint8_t host_id,uint8_t reg_add,uint8_t data)150 void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
151 {
152 (void)host_id;
153 uint8_t i2c_sel = regi2c_enable_block(block);
154
155 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
156 uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
157 | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
158 | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register;
159 | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
160 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
161 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
162
163 }
164
regi2c_write_mask_impl(uint8_t block,uint8_t host_id,uint8_t reg_add,uint8_t msb,uint8_t lsb,uint8_t data)165 void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
166 {
167 (void)host_id;
168 assert(msb - lsb < 8);
169 uint8_t i2c_sel = regi2c_enable_block(block);
170
171 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
172 /*Read the i2c bus register*/
173 uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
174 | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
175 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
176 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
177 temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
178 /*Write the i2c bus register*/
179 temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
180 temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
181 temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
182 | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
183 | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S)
184 | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
185 REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
186 while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
187 }
188
