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Searched refs:HAL_ASSERT (Results 1 – 25 of 158) sorted by relevance

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/hal_espressif-latest/components/hal/esp32h2/include/hal/
Decdsa_ll.h87 HAL_ASSERT(false && "Unsupported interrupt type"); in ecdsa_ll_enable_intr()
107 HAL_ASSERT(false && "Unsupported interrupt type"); in ecdsa_ll_disable_intr()
127 HAL_ASSERT(false && "Unsupported interrupt type"); in ecdsa_ll_clear_intr()
147 HAL_ASSERT(false && "Unsupported mode"); in ecdsa_ll_set_mode()
167 HAL_ASSERT(false && "Unsupported curve"); in ecdsa_ll_set_curve()
187 HAL_ASSERT(false && "Unsupported curve"); in ecdsa_ll_set_z_mode()
210 HAL_ASSERT(false && "Unsupported state"); in ecdsa_ll_set_stage()
240 HAL_ASSERT(false && "Unsupported type"); in ecdsa_ll_sha_set_type()
260 HAL_ASSERT(false && "Unsupported type"); in ecdsa_ll_sha_set_mode()
304 HAL_ASSERT(false && "Invalid parameter"); in ecdsa_ll_write_param()
[all …]
Dcache_ll.h43 HAL_ASSERT(cache_id == 0); in cache_ll_l1_get_bus()
51 HAL_ASSERT(0); //Out of region in cache_ll_l1_get_bus()
68 HAL_ASSERT(cache_id == 0); in cache_ll_l1_enable_bus()
70 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
90 HAL_ASSERT(cache_id == 0); in cache_ll_l1_disable_bus()
92 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
Dadc_ll.h319 HAL_ASSERT(false && "unsupported clock"); in adc_ll_digi_clk_sel()
374 HAL_ASSERT(false); in adc_ll_digi_filter_set_factor()
558 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_ll_calibration_prepare()
574 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_ll_calibration_finish()
588 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_ll_set_calibration_param()
608 HAL_ASSERT(bits == ADC_BITWIDTH_12 || bits == ADC_BITWIDTH_DEFAULT); in adc_oneshot_ll_set_output_bits()
621 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_oneshot_ll_set_channel()
634 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_oneshot_ll_disable_channel()
683 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_oneshot_ll_get_raw_result()
701 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_oneshot_ll_raw_check_valid()
[all …]
Decc_ll.h93 HAL_ASSERT(false && "Unsupported mode"); in ecc_ll_set_mode()
108 HAL_ASSERT(false && "Unsupported curve"); in ecc_ll_set_curve()
123 HAL_ASSERT(false && "Unsupported curve"); in ecc_ll_set_mod_base()
152 HAL_ASSERT(false && "Invalid parameter"); in ecc_ll_write_param()
215 HAL_ASSERT(false && "Invalid parameter"); in ecc_ll_read_param()
/hal_espressif-latest/components/hal/
Dmmu_hal.c50 HAL_ASSERT(shift_code); in mmu_hal_pages_to_bytes()
70 HAL_ASSERT(shift_code); in mmu_hal_bytes_to_pages()
78 HAL_ASSERT(vaddr % page_size_in_bytes == 0); in mmu_hal_map_region()
79 HAL_ASSERT(paddr % page_size_in_bytes == 0); in mmu_hal_map_region()
80 HAL_ASSERT(mmu_ll_check_valid_paddr_region(mmu_id, paddr, len)); in mmu_hal_map_region()
81 …HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, len, MMU_VADDR_DATA | MMU_VADDR_INS… in mmu_hal_map_region()
102 HAL_ASSERT(vaddr % page_size_in_bytes == 0); in mmu_hal_unmap_region()
103 …HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, len, MMU_VADDR_DATA | MMU_VADDR_INS… in mmu_hal_unmap_region()
117 …HAL_ASSERT(mmu_hal_check_valid_ext_vaddr_region(mmu_id, vaddr, 1, MMU_VADDR_DATA | MMU_VADDR_INSTR… in mmu_hal_vaddr_to_paddr()
135 HAL_ASSERT(mmu_ll_check_valid_paddr_region(mmu_id, paddr, 1)); in mmu_hal_paddr_to_vaddr()
Dusb_dwc_hal.c126 HAL_ASSERT(core_id == CORE_REG_GSNPSID); in usb_dwc_hal_init()
206 …HAL_ASSERT((fifo_config.rx_fifo_lines + fifo_config.nptx_fifo_lines + fifo_config.ptx_fifo_lines) … in usb_dwc_hal_set_fifo_bias()
210 HAL_ASSERT(!hal->channels.hdls[i]->flags.active); in usb_dwc_hal_set_fifo_bias()
227 HAL_ASSERT(hal && mps_limits); in usb_dwc_hal_get_mps_limits()
228 HAL_ASSERT(hal->flags.fifo_sizes_set); in usb_dwc_hal_get_mps_limits()
260 …HAL_ASSERT(hal->flags.fifo_sizes_set); //FIFO sizes should be set befor attempting to allocate a … in usb_dwc_hal_chan_alloc()
274 HAL_ASSERT(chan_idx != -1); in usb_dwc_hal_chan_alloc()
299 HAL_ASSERT(!chan_obj->flags.active); in usb_dwc_hal_chan_free()
305 HAL_ASSERT(hal->channels.num_allocd >= 0); in usb_dwc_hal_chan_free()
313 HAL_ASSERT(!chan_obj->flags.active); in usb_dwc_hal_chan_set_ep_char()
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Decdsa_hal.c97 HAL_ASSERT(false && "Incorrect length"); in ecdsa_hal_gen_signature()
101 HAL_ASSERT(false && "Mismatch in SHA configuration"); in ecdsa_hal_gen_signature()
105 HAL_ASSERT(false && "Incorrect ECDSA state"); in ecdsa_hal_gen_signature()
122 HAL_ASSERT(false && "Incorrect length"); in ecdsa_hal_verify_signature()
126 HAL_ASSERT(false && "Incorrect ECDSA state"); in ecdsa_hal_verify_signature()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dmemprot_ll.h47 …HAL_ASSERT((REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1) && "Value … in memprot_ll_set_iram0_dram0_split_line_lock()
108 …HAL_ASSERT((expected == memprot_ll_icache_set_permissions(r, w, x)) && "Value not stored to requir… in memprot_ll_icache_set_pms_area_0()
117 …HAL_ASSERT((expected == memprot_ll_icache_set_permissions(r, w, x)) && "Value not stored to requir… in memprot_ll_icache_set_pms_area_1()
222 HAL_ASSERT((REG_READ(sensitive_reg) == regval) && "Value not stored to required register"); in memprot_ll_set_iram0_split_line()
285 …HAL_ASSERT((REG_READ(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG) == 1) && "Value not stored to req… in memprot_ll_iram0_set_pms_lock()
316 …HAL_ASSERT((expected == memprot_ll_iram0_set_permissions(r, w, x)) && "Value not stored to require… in memprot_ll_iram0_set_pms_area_0()
325 …HAL_ASSERT((expected == memprot_ll_iram0_set_permissions(r, w, x)) && "Value not stored to require… in memprot_ll_iram0_set_pms_area_1()
334 …HAL_ASSERT((expected == memprot_ll_iram0_set_permissions(r, w, x)) && "Value not stored to require… in memprot_ll_iram0_set_pms_area_2()
343 …HAL_ASSERT((expected == memprot_ll_iram0_set_permissions(r, w, x)) && "Value not stored to require… in memprot_ll_iram0_set_pms_area_3()
389 …HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to requi… in memprot_ll_iram0_set_monitor_lock()
[all …]
Dcache_ll.h51 HAL_ASSERT(cache_id == 0 || cache_id == 1); in cache_ll_l1_is_cache_enabled()
80 HAL_ASSERT(cache_id == 0 || cache_id == 1); in cache_ll_l1_get_bus()
89 HAL_ASSERT(0); //Out of region in cache_ll_l1_get_bus()
106 HAL_ASSERT(cache_id == 0 || cache_id == 1); in cache_ll_l1_enable_bus()
108 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
138 HAL_ASSERT(cache_id == 0 || cache_id == 1); in cache_ll_l1_get_enabled_bus()
167 HAL_ASSERT(cache_id == 0 || cache_id == 1); in cache_ll_l1_disable_bus()
169 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
Dmmu_ll.h79 HAL_ASSERT(size == MMU_PAGE_64KB); in mmu_ll_set_page_size()
175 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_write_entry()
192 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_read_entry()
207 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_set_entry_invalid()
236 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()
252 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_get_entry_target()
269 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_entry_id_to_paddr_base()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dcache_ll.h30 HAL_ASSERT(cache_id == 0 || cache_id == 1); in cache_ll_l1_enable_cache()
70 HAL_ASSERT(cache_id == 0 || cache_id == 1); in cache_ll_l1_is_cache_enabled()
97 HAL_ASSERT(cache_id == 0 || cache_id == 1); in cache_ll_l1_get_bus()
102 HAL_ASSERT(false); //out of range in cache_ll_l1_get_bus()
113 …HAL_ASSERT(vaddr_end < DRAM1_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, se… in cache_ll_l1_get_bus()
116 …HAL_ASSERT(vaddr_end < DROM0_CACHE_ADDRESS_HIGH); //out of range, vaddr should be consecutive, se… in cache_ll_l1_get_bus()
119 HAL_ASSERT(false); in cache_ll_l1_get_bus()
138 HAL_ASSERT(cache_id == 0 || cache_id == 1); in cache_ll_l1_enable_bus()
173 HAL_ASSERT(cache_id == 0 || cache_id == 1); in cache_ll_l1_get_enabled_bus()
205 HAL_ASSERT(cache_id == 0 || cache_id == 1); in cache_ll_l1_disable_bus()
Dmmu_ll.h174 HAL_ASSERT(false); in mmu_ll_get_entry_id()
228 HAL_ASSERT(false); in mmu_ll_write_entry()
254 HAL_ASSERT(false); in mmu_ll_read_entry()
269 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_set_entry_invalid()
279 HAL_ASSERT(false); in mmu_ll_set_entry_invalid()
308 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()
327 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_get_entry_target()
328 HAL_ASSERT(mmu_ll_check_entry_valid(mmu_id, entry_id)); in mmu_ll_get_entry_target()
344 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_entry_id_to_paddr_base()
452 HAL_ASSERT(false); in mmu_ll_entry_id_to_vaddr_base()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dcache_ll.h48 HAL_ASSERT(cache_id == 0); in cache_ll_l1_is_cache_enabled()
68 HAL_ASSERT(cache_id == 0); in cache_ll_l1_get_bus()
77 HAL_ASSERT(0); //Out of region in cache_ll_l1_get_bus()
94 HAL_ASSERT(cache_id == 0); in cache_ll_l1_enable_bus()
96 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
116 HAL_ASSERT(cache_id == 0); in cache_ll_l1_disable_bus()
118 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
Dmmu_ll.h155 HAL_ASSERT(shift_code); in mmu_ll_get_entry_id()
190 HAL_ASSERT(shift_code); in mmu_ll_format_paddr()
208 HAL_ASSERT(target == MMU_TARGET_FLASH0); in mmu_ll_write_entry()
209 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_write_entry()
225 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_read_entry()
240 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_set_entry_invalid()
269 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()
299 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_entry_id_to_paddr_base()
314 HAL_ASSERT(shift_code); in mmu_ll_entry_id_to_paddr_base()
371 HAL_ASSERT(shift_code); in mmu_ll_entry_id_to_vaddr_base()
Decc_ll.h54 HAL_ASSERT(false && "Unsupported mode"); in ecc_ll_set_mode()
69 HAL_ASSERT(false && "Unsupported curve"); in ecc_ll_set_curve()
89 HAL_ASSERT(false && "Invalid parameter"); in ecc_ll_write_param()
138 HAL_ASSERT(false && "Invalid parameter"); in ecc_ll_read_param()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dcache_ll.h49 HAL_ASSERT(cache_id == 0); in cache_ll_l1_is_cache_enabled()
69 HAL_ASSERT(cache_id == 0); in cache_ll_l1_get_bus()
78 HAL_ASSERT(0); //Out of region in cache_ll_l1_get_bus()
95 HAL_ASSERT(cache_id == 0); in cache_ll_l1_enable_bus()
97 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
117 HAL_ASSERT(cache_id == 0); in cache_ll_l1_disable_bus()
119 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
Dmmu_ll.h79 HAL_ASSERT(size == MMU_PAGE_64KB); in mmu_ll_set_page_size()
175 HAL_ASSERT(target == MMU_TARGET_FLASH0); in mmu_ll_write_entry()
176 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_write_entry()
192 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_read_entry()
207 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_set_entry_invalid()
236 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()
252 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_get_entry_target()
268 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_entry_id_to_paddr_base()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dcache_ll.h43 HAL_ASSERT(cache_id == 0); in cache_ll_l1_get_bus()
51 HAL_ASSERT(0); //Out of region in cache_ll_l1_get_bus()
68 HAL_ASSERT(cache_id == 0); in cache_ll_l1_enable_bus()
70 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_enable_bus()
90 HAL_ASSERT(cache_id == 0); in cache_ll_l1_disable_bus()
92 … HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); in cache_ll_l1_disable_bus()
Dadc_ll.h319 HAL_ASSERT(false && "unsupported clock"); in adc_ll_digi_clk_sel()
374 HAL_ASSERT(false); in adc_ll_digi_filter_set_factor()
558 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_ll_calibration_prepare()
574 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_ll_calibration_finish()
588 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_ll_set_calibration_param()
608 HAL_ASSERT(bits == ADC_BITWIDTH_12 || bits == ADC_BITWIDTH_DEFAULT); in adc_oneshot_ll_set_output_bits()
621 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_oneshot_ll_set_channel()
634 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_oneshot_ll_disable_channel()
683 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_oneshot_ll_get_raw_result()
701 HAL_ASSERT(adc_n == ADC_UNIT_1); in adc_oneshot_ll_raw_check_valid()
[all …]
Decc_ll.h65 HAL_ASSERT(false && "Unsupported mode"); in ecc_ll_set_mode()
80 HAL_ASSERT(false && "Unsupported curve"); in ecc_ll_set_curve()
100 HAL_ASSERT(false && "Invalid parameter"); in ecc_ll_write_param()
149 HAL_ASSERT(false && "Invalid parameter"); in ecc_ll_read_param()
/hal_espressif-latest/components/hal/platform_port/include/hal/
Dassert.h35 #define HAL_ASSERT(__e) ((void)(__e)) macro
37 #define HAL_ASSERT(__e) (__builtin_expect(!!(__e), 1) ? (void)0 : abort()) macro
39 #define HAL_ASSERT(__e) (__builtin_expect(!!(__e), 1) ? (void)0 : __assert_func(__FILE__, __LINE__,… macro
41 #define HAL_ASSERT(__e) ((void)(__e)) macro
/hal_espressif-latest/components/hal/esp32c6/
Dmodem_clock_hal.c24 HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); in modem_clock_hal_set_clock_domain_icg_bitmap()
58 HAL_ASSERT(0); in modem_clock_hal_set_clock_domain_icg_bitmap()
64 HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX); in modem_clock_hal_get_clock_domain_icg_bitmap()
99 HAL_ASSERT(0); in modem_clock_hal_get_clock_domain_icg_bitmap()
140 HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); in modem_clock_hal_select_ble_rtc_timer_lpclk_source()
166 HAL_ASSERT(0); in modem_clock_hal_select_ble_rtc_timer_lpclk_source()
180 HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); in modem_clock_hal_select_coex_lpclk_source()
206 HAL_ASSERT(0); in modem_clock_hal_select_coex_lpclk_source()
220 HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); in modem_clock_hal_select_wifi_lpclk_source()
246 HAL_ASSERT(0); in modem_clock_hal_select_wifi_lpclk_source()
[all …]
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dmmu_ll.h79 HAL_ASSERT(size == MMU_PAGE_64KB); in mmu_ll_set_page_size()
157 HAL_ASSERT(false); in mmu_ll_get_entry_id()
193 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_write_entry()
210 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_read_entry()
225 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_set_entry_invalid()
254 HAL_ASSERT(entry_id < MMU_ENTRY_NUM); in mmu_ll_check_entry_valid()
269 HAL_ASSERT(mmu_ll_check_entry_valid(mmu_id, entry_id)); in mmu_ll_get_entry_target()
371 HAL_ASSERT(false); in mmu_ll_entry_id_to_vaddr_base()
/hal_espressif-latest/components/hal/esp32h2/
Dmodem_clock_hal.c56 HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); in modem_clock_hal_select_ble_rtc_timer_lpclk_source()
82 HAL_ASSERT(0); in modem_clock_hal_select_ble_rtc_timer_lpclk_source()
96 HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); in modem_clock_hal_select_coex_lpclk_source()
122 HAL_ASSERT(0); in modem_clock_hal_select_coex_lpclk_source()
/hal_espressif-latest/components/hal/esp32c2/
Drtc_cntl_hal.c23 HAL_ASSERT(elem != NULL); in rtc_cntl_hal_dma_link_init()
24 HAL_ASSERT(buff != NULL); in rtc_cntl_hal_dma_link_init()
25 HAL_ASSERT(size >= RTC_CNTL_HAL_LINK_BUF_SIZE_MIN); in rtc_cntl_hal_dma_link_init()

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