1 /*
2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 // The HAL layer for MODEM CLOCK (ESP32-H2 specific part)
8 #include <stdbool.h>
9 #include "esp_attr.h"
10 #include "soc/soc.h"
11 #include "hal/modem_clock_hal.h"
12 #include "hal/lp_clkrst_ll.h"
13 #include "hal/modem_clock_types.h"
14 #include "hal/assert.h"
15
16 typedef enum {
17 MODEM_CLOCK_XTAL32K_CODE = 0,
18 MODEM_CLOCK_RC32K_CODE = 1,
19 MODEM_CLOCK_EXT32K_CODE = 2
20 } modem_clock_32k_clk_src_code_t;
21
modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t * hal,bool enable)22 void IRAM_ATTR modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
23 {
24 modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
25 modem_syscon_ll_enable_fe_32m_clock(hal->syscon_dev, enable);
26 }
27
modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_context_t * hal,bool enable)28 void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_context_t *hal, bool enable)
29 {
30 modem_lpcon_ll_enable_fe_mem_clock(hal->lpcon_dev, enable);
31 modem_syscon_ll_enable_fe_sdm_clock(hal->syscon_dev, enable);
32 modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable);
33 modem_syscon_ll_enable_fe_16m_clock(hal->syscon_dev, enable);
34 }
35
modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t * hal,uint32_t divider)36 void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider)
37 {
38 lp_clkrst_ll_set_ble_rtc_timer_divisor_value(&LP_CLKRST, divider);
39 }
40
modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t * hal,bool enable)41 void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable)
42 {
43 // No clock gate on ESP32-H2
44 }
45
modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t * hal)46 void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal)
47 {
48 lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, false);
49 lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, false);
50 lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, false);
51 lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, false);
52 }
53
modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t * hal,modem_clock_lpclk_src_t src)54 void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
55 {
56 HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
57
58 switch (src)
59 {
60 case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
61 lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, true);
62 break;
63 case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
64 lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, true);
65 break;
66 case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
67 lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, true);
68 break;
69 case MODEM_CLOCK_LPCLK_SRC_RC32K:
70 lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
71 lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
72 break;
73 case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
74 lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
75 lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
76 break;
77 case MODEM_CLOCK_LPCLK_SRC_EXT32K:
78 lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
79 lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
80 break;
81 default:
82 HAL_ASSERT(0);
83 }
84 }
85
modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t * hal)86 void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal)
87 {
88 modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, false);
89 modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, false);
90 modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, false);
91 modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, false);
92 }
93
modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t * hal,modem_clock_lpclk_src_t src)94 void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
95 {
96 HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
97
98 switch (src)
99 {
100 case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
101 modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true);
102 break;
103 case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
104 modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, true);
105 break;
106 case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
107 modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, true);
108 break;
109 case MODEM_CLOCK_LPCLK_SRC_RC32K:
110 modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
111 lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
112 break;
113 case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
114 modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
115 lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
116 break;
117 case MODEM_CLOCK_LPCLK_SRC_EXT32K:
118 modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
119 lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
120 break;
121 default:
122 HAL_ASSERT(0);
123 }
124 }
125
