Home
last modified time | relevance | path

Searched refs:GET_PERI_REG_MASK (Results 1 – 25 of 43) sorted by relevance

12

/hal_espressif-latest/components/esp_hw_support/port/esp32s2/
Drtc_time.c38 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { in rtc_clk_cal_internal_oneoff()
44 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) in rtc_clk_cal_internal_oneoff()
45 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); in rtc_clk_cal_internal_oneoff()
75 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_cal_internal_oneoff()
79 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { in rtc_clk_cal_internal_oneoff()
101 …if (cali_slowclk_cycles == 0 || !GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYC… in rtc_clk_cal_internal_cycling()
110 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_CYCLING_DATA_VLD)); in rtc_clk_cal_internal_cycling()
247 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
/hal_espressif-latest/components/esp_hw_support/port/esp32c2/
Drtc_time.c64 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { in rtc_clk_cal_internal()
70 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) in rtc_clk_cal_internal()
71 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); in rtc_clk_cal_internal()
101 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_cal_internal()
105 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { in rtc_clk_cal_internal()
179 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
Drtc_time.c68 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { in rtc_clk_cal_internal()
74 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) in rtc_clk_cal_internal()
75 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); in rtc_clk_cal_internal()
105 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_cal_internal()
109 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { in rtc_clk_cal_internal()
182 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
/hal_espressif-latest/components/esp_hw_support/port/esp32s3/
Drtc_time.c66 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { in rtc_clk_cal_internal()
72 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) in rtc_clk_cal_internal()
73 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); in rtc_clk_cal_internal()
103 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_cal_internal()
107 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { in rtc_clk_cal_internal()
181 while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) { in rtc_clk_wait_for_slow_cycle()
/hal_espressif-latest/components/esp_hw_support/port/esp32c6/
Drtc_time.c114 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { in rtc_clk_cal_internal()
120 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) in rtc_clk_cal_internal()
121 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); in rtc_clk_cal_internal()
151 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_cal_internal()
164 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { in rtc_clk_cal_internal()
/hal_espressif-latest/components/esp_hw_support/port/esp32h2/
Drtc_time.c114 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) { in rtc_clk_cal_internal()
120 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) in rtc_clk_cal_internal()
121 && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)); in rtc_clk_cal_internal()
151 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_cal_internal()
164 if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) { in rtc_clk_cal_internal()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dcache_ll.h232 return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask); in cache_ll_l1_get_access_error_intr_status()
234 return GET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ST_REG, mask); in cache_ll_l1_get_access_error_intr_status()
270 return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask); in cache_ll_l1_get_illegal_error_intr_status()
Dclk_tree_ll.h157 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in clk_ll_rc_fast_is_enabled()
191 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in clk_ll_rc_fast_d256_is_enabled()
217 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_is_enabled()
695 uint32_t pll_reg = GET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | in clk_ll_bbpll_set_frequency_for_mspi_tuning()
Dgpio_ll.h469 …return !GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK… in gpio_ll_deep_sleep_hold_is_en()
509 return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - 21)); in gpio_ll_is_digital_io_hold()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dcache_ll.h164 return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask); in cache_ll_l1_get_access_error_intr_status()
199 return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask); in cache_ll_l1_get_illegal_error_intr_status()
Dgpio_ll.h419 …return !GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK… in gpio_ll_deep_sleep_hold_is_en()
467 return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num)); in gpio_ll_is_digital_io_hold()
706 …return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio… in gpio_ll_deepsleep_wakeup_is_enabled()
Dclk_tree_ll.h88 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in clk_ll_rc_fast_is_enabled()
122 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in clk_ll_rc_fast_d256_is_enabled()
148 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_is_enabled()
Drtc_cntl_ll.h30 return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS); in rtc_cntl_ll_gpio_get_wakeup_status()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dcache_ll.h165 return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask); in cache_ll_l1_get_access_error_intr_status()
200 return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask); in cache_ll_l1_get_illegal_error_intr_status()
Dgpio_ll.h442 …return !GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK… in gpio_ll_deep_sleep_hold_is_en()
490 return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num)); in gpio_ll_is_digital_io_hold()
733 …return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio… in gpio_ll_deepsleep_wakeup_is_enabled()
Dclk_tree_ll.h155 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in clk_ll_rc_fast_is_enabled()
189 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in clk_ll_rc_fast_d256_is_enabled()
215 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_is_enabled()
Drtc_cntl_ll.h30 return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS); in rtc_cntl_ll_gpio_get_wakeup_status()
/hal_espressif-latest/components/esp_hw_support/port/esp32/
Drtc_time.c88 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) && in rtc_clk_cal_internal()
174 while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { in rtc_clk_wait_for_slow_cycle()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dclk_tree_ll.h261 return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K); in clk_ll_xtal32k_is_enabled()
289 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in clk_ll_rc_fast_is_enabled()
323 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in clk_ll_rc_fast_d256_is_enabled()
349 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_is_enabled()
Dgpio_ll.h599 …return !GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK… in gpio_ll_deep_sleep_hold_is_en()
651 return GET_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, mask); in gpio_ll_is_digital_io_hold()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dgpio_ll.h443 …return !GET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD) && GET_PERI_REG_MASK… in gpio_ll_deep_sleep_hold_is_en()
483 return GET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, BIT(gpio_num - 21)); in gpio_ll_is_digital_io_hold()
Dclk_tree_ll.h241 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; in clk_ll_rc_fast_is_enabled()
275 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; in clk_ll_rc_fast_d256_is_enabled()
301 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M); in clk_ll_rc_fast_digi_is_enabled()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dcache_ll.h138 return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask); in cache_ll_l1_get_access_error_intr_status()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dcache_ll.h138 return GET_PERI_REG_MASK(EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG, mask); in cache_ll_l1_get_access_error_intr_status()
/hal_espressif-latest/components/soc/esp32/include/soc/
Dsoc.h130 #define GET_PERI_REG_MASK(reg, mask) ({ … macro
131 …ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); …

12