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Searched refs:DPORT_PRO_CACHE_CTRL_REG (Results 1 – 5 of 5) sorted by relevance

/hal_espressif-latest/components/esp_psram/esp32/
Desp_psram_extram_cache.c36 if (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE)==0) { in esp_psram_extram_writeback_cache()
38 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S); in esp_psram_extram_writeback_cache()
70 DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S); in esp_psram_extram_writeback_cache()
Desp_psram_impl_quad.c1109 DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT); in psram_cache_init()
1112 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL); in psram_cache_init()
1115 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT); in psram_cache_init()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dcache_ll.h33 DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE); in cache_ll_l1_enable_cache()
51 DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE); in cache_ll_l1_disable_cache()
75 enabled = DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE); in cache_ll_l1_is_cache_enabled()
/hal_espressif-latest/components/esp_psram/esp32s2/
Desp_psram_impl_quad.c534 DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT); in psram_cache_init()
537 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL); in psram_cache_init()
540 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT); in psram_cache_init()
/hal_espressif-latest/components/soc/esp32/include/soc/
Ddport_reg.h175 #define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) macro