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Searched refs:WRITE_PERI_REG (Results 1 – 25 of 53) sorted by relevance

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/hal_espressif-3.5.0/components/esp_hw_support/test/
Dtest_unal_dma.c55 WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S)); in dmaMemcpy()
56 WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S)); in dmaMemcpy()
57 WRITE_PERI_REG(GPIO_FUNC5_OUT_SEL_CFG_REG, (150 << GPIO_FUNC0_OUT_SEL_S)); in dmaMemcpy()
58 WRITE_PERI_REG(GPIO_FUNC16_OUT_SEL_CFG_REG, (151 << GPIO_FUNC0_OUT_SEL_S)); in dmaMemcpy()
59 WRITE_PERI_REG(GPIO_FUNC17_OUT_SEL_CFG_REG, (152 << GPIO_FUNC0_OUT_SEL_S)); in dmaMemcpy()
60 WRITE_PERI_REG(GPIO_FUNC18_OUT_SEL_CFG_REG, (153 << GPIO_FUNC0_OUT_SEL_S)); in dmaMemcpy()
61 WRITE_PERI_REG(GPIO_FUNC19_OUT_SEL_CFG_REG, (154 << GPIO_FUNC0_OUT_SEL_S)); in dmaMemcpy()
62 WRITE_PERI_REG(GPIO_FUNC20_OUT_SEL_CFG_REG, (155 << GPIO_FUNC0_OUT_SEL_S)); in dmaMemcpy()
63 WRITE_PERI_REG(GPIO_FUNC26_OUT_SEL_CFG_REG, (156 << GPIO_FUNC0_OUT_SEL_S)); //RS in dmaMemcpy()
64 WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, (I2S0O_WS_OUT_IDX << GPIO_FUNC0_OUT_SEL_S)); in dmaMemcpy()
[all …]
Dtest_ahb_arb.c60 WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S)); in lcdIfaceInit()
61 WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S)); in lcdIfaceInit()
62 WRITE_PERI_REG(GPIO_FUNC5_OUT_SEL_CFG_REG, (150 << GPIO_FUNC0_OUT_SEL_S)); in lcdIfaceInit()
63 WRITE_PERI_REG(GPIO_FUNC16_OUT_SEL_CFG_REG, (151 << GPIO_FUNC0_OUT_SEL_S)); in lcdIfaceInit()
64 WRITE_PERI_REG(GPIO_FUNC17_OUT_SEL_CFG_REG, (152 << GPIO_FUNC0_OUT_SEL_S)); in lcdIfaceInit()
65 WRITE_PERI_REG(GPIO_FUNC18_OUT_SEL_CFG_REG, (153 << GPIO_FUNC0_OUT_SEL_S)); in lcdIfaceInit()
66 WRITE_PERI_REG(GPIO_FUNC19_OUT_SEL_CFG_REG, (154 << GPIO_FUNC0_OUT_SEL_S)); in lcdIfaceInit()
67 WRITE_PERI_REG(GPIO_FUNC20_OUT_SEL_CFG_REG, (155 << GPIO_FUNC0_OUT_SEL_S)); in lcdIfaceInit()
68 WRITE_PERI_REG(GPIO_FUNC26_OUT_SEL_CFG_REG, (156 << GPIO_FUNC0_OUT_SEL_S)); //RS in lcdIfaceInit()
69 WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, (I2S0O_WS_OUT_IDX << GPIO_FUNC0_OUT_SEL_S)); in lcdIfaceInit()
[all …]
Dtest_fastbus.c52 WRITE_PERI_REG(UART_FIFO_REG(1), x ^ xor); in tskOne()
98 WRITE_PERI_REG(UART_FIFO_REG(1), x ^ xor); in tskTwo()
120 WRITE_PERI_REG(UART_CONF1_REG(1), reg_val);
121 WRITE_PERI_REG(UART_CLKDIV_REG(1), 0x30); //semi-random
/hal_espressif-3.5.0/components/esp_system/port/soc/esp32s2/
Dsystem_internal.c85 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
86 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
87 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
88 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
89 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
90 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
/hal_espressif-3.5.0/components/esp_system/port/soc/esp32h2/
Dsystem_internal.c88 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
89 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
90 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
91 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
92 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
93 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
/hal_espressif-3.5.0/components/esp_system/port/soc/esp32/
Dsystem_internal.c105 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
106 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
107 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
108 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
109 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
110 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
/hal_espressif-3.5.0/components/esp_system/port/soc/esp32c3/
Dsystem_internal.c89 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
90 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
91 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
92 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
93 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
94 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
/hal_espressif-3.5.0/components/esp_system/port/soc/esp32s3/
Dsystem_internal.c89 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
90 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
91 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
92 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
93 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
94 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
/hal_espressif-3.5.0/components/spi_flash/esp32/
Dspi_flash_rom_patch.c127 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_CE); in esp_rom_spiflash_erase_chip_internal()
147 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff); in esp_rom_spiflash_erase_sector_internal()
148 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_SE); in esp_rom_spiflash_erase_sector_internal()
162 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff); in esp_rom_spiflash_erase_block_internal()
163 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_BE); in esp_rom_spiflash_erase_block_internal()
200 …WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | ( ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE… in esp_rom_spiflash_program_page_internal()
203 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++); in esp_rom_spiflash_program_page_internal()
208 …WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | (temp_bl << ESP_ROM_SPIFLASH_BYTES… in esp_rom_spiflash_program_page_internal()
212 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++); in esp_rom_spiflash_program_page_internal()
217 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_PP); in esp_rom_spiflash_program_page_internal()
[all …]
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32/
Drtc_wdt.c18 WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE); in rtc_wdt_protect_off()
23 WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0); in rtc_wdt_protect_on()
75 WRITE_PERI_REG(RTC_CNTL_WDTCONFIG1_REG, timeout); in rtc_wdt_set_time()
77 WRITE_PERI_REG(RTC_CNTL_WDTCONFIG2_REG, timeout); in rtc_wdt_set_time()
79 WRITE_PERI_REG(RTC_CNTL_WDTCONFIG3_REG, timeout); in rtc_wdt_set_time()
81 WRITE_PERI_REG(RTC_CNTL_WDTCONFIG4_REG, timeout); in rtc_wdt_set_time()
/hal_espressif-3.5.0/components/esp_system/
Dcrosscore_int.c66 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); in esp_crosscore_isr()
68 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0); in esp_crosscore_isr()
71 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); in esp_crosscore_isr()
133 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); in esp_crosscore_int_send()
135 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1); in esp_crosscore_int_send()
138 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); in esp_crosscore_int_send()
/hal_espressif-3.5.0/components/bootloader_support/src/
Dbootloader_random_esp32.c53 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD); in bootloader_random_enable()
54 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD); in bootloader_random_enable()
55 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD); in bootloader_random_enable()
56 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD); in bootloader_random_enable()
/hal_espressif-3.5.0/components/ulp/ulp_riscv/include/ulp_riscv/
Dulp_riscv_register_ops.h109 #define WRITE_PERI_REG(addr, val) ({ … macro
115 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
120 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
137 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
/hal_espressif-3.5.0/components/soc/esp32s2/include/soc/
Dsoc.h203 #define WRITE_PERI_REG(addr, val) ({ … macro
204 …ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); …
211 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
217 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
235 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
/hal_espressif-3.5.0/components/soc/esp32/include/soc/
Dsoc.h174 #define WRITE_PERI_REG(addr, val) ({ … macro
175 …ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); …
182 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
188 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
206 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32s2/
Drtc_wdt.c19 WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE); in rtc_wdt_protect_off()
24 WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0); in rtc_wdt_protect_on()
93 WRITE_PERI_REG(get_addr_reg(stage), timeout); in rtc_wdt_set_time()
Dspiram_psram.c223 WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); in psram_exec_cmd()
224 WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1); in psram_exec_cmd()
225 WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2); in psram_exec_cmd()
226 WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl); in psram_exec_cmd()
483 WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK); in psram_clock_set()
486 WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits); in psram_clock_set()
/hal_espressif-3.5.0/components/soc/esp32c3/include/soc/
Dsoc.h161 #define WRITE_PERI_REG(addr, val) ({ … macro
167 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
172 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
187 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
/hal_espressif-3.5.0/components/soc/esp32h2/include/soc/
Dsoc.h184 #define WRITE_PERI_REG(addr, val) ({ … macro
190 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
195 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
210 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
/hal_espressif-3.5.0/components/soc/esp32s3/include/soc/
Dsoc.h194 #define WRITE_PERI_REG(addr, val) ({ … macro
200 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
205 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
220 …(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) …
/hal_espressif-3.5.0/components/hal/esp32h2/include/hal/
Drtc_cntl_ll.h28 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
29 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-3.5.0/components/hal/esp32/include/hal/
Drtc_cntl_ll.h27 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
28 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-3.5.0/components/hal/esp32s2/include/hal/
Drtc_cntl_ll.h27 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
28 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-3.5.0/components/hal/esp32c3/include/hal/
Drtc_cntl_ll.h28 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
29 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-3.5.0/components/esp_hw_support/port/esp32s3/
Dspiram_psram.c184 WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); in psram_exec_cmd()
185 WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1); in psram_exec_cmd()
186 WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2); in psram_exec_cmd()
187 WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl); in psram_exec_cmd()

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