1 // Copyright 2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <string.h>
16 #include "sdkconfig.h"
17 #include "esp_system.h"
18 #include "esp_private/system_internal.h"
19 #include "esp_attr.h"
20 #include "esp_efuse.h"
21 #include "esp_log.h"
22 #include "riscv/riscv_interrupts.h"
23 #include "riscv/interrupt.h"
24 #include "esp_rom_uart.h"
25 #include "soc/gpio_reg.h"
26 #include "soc/rtc_cntl_reg.h"
27 #include "soc/timer_group_reg.h"
28 #include "soc/cpu.h"
29 #include "soc/rtc.h"
30 #include "soc/rtc_periph.h"
31 #include "soc/syscon_reg.h"
32 #include "soc/system_reg.h"
33 #include "soc/uart_reg.h"
34 #include "hal/wdt_hal.h"
35 #include "cache_err_int.h"
36
37 #include "esp32c3/rom/cache.h"
38 #include "esp32c3/rom/rtc.h"
39
40 /* "inner" restart function for after RTOS, interrupts & anything else on this
41 * core are already stopped. Stalls other core, resets hardware,
42 * triggers restart.
43 */
esp_restart_noos(void)44 void IRAM_ATTR esp_restart_noos(void)
45 {
46 // Disable interrupts
47 riscv_global_interrupts_disable();
48 // Enable RTC watchdog for 1 second
49 wdt_hal_context_t rtc_wdt_ctx;
50 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
51 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
52 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
53 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
54 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
55 //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
56 wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
57 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
58
59 // Reset and stall the other CPU.
60 // CPU must be reset before stalling, in case it was running a s32c1i
61 // instruction. This would cause memory pool to be locked by arbiter
62 // to the stalled CPU, preventing current CPU from accessing this pool.
63 const uint32_t core_id = cpu_hal_get_core_id();
64 #if !CONFIG_FREERTOS_UNICORE
65 const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
66 esp_cpu_reset(other_core_id);
67 esp_cpu_stall(other_core_id);
68 #endif
69
70 // Disable TG0/TG1 watchdogs
71 wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
72 wdt_hal_write_protect_disable(&wdt0_context);
73 wdt_hal_disable(&wdt0_context);
74 wdt_hal_write_protect_enable(&wdt0_context);
75
76 wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
77 wdt_hal_write_protect_disable(&wdt1_context);
78 wdt_hal_disable(&wdt1_context);
79 wdt_hal_write_protect_enable(&wdt1_context);
80
81 // Flush any data left in UART FIFOs
82 esp_rom_uart_tx_wait_idle(0);
83 esp_rom_uart_tx_wait_idle(1);
84 // Disable cache
85 Cache_Disable_ICache();
86
87 // 2nd stage bootloader reconfigures SPI flash signals.
88 // Reset them to the defaults expected by ROM.
89 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
90 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
91 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
92 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
93 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
94 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
95
96 // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
97 SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
98 SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST |
99 SYSTEM_BT_RST | SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST |
100 SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST |
101 SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | BLE_REG_REST_BIT
102 |BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
103
104
105 REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
106
107 // Reset uart0 core first, then reset apb side.
108 // rom will clear this bit, as well as SYSTEM_UART_RST
109 SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M);
110
111 // Reset timer/spi/uart
112 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
113 SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
114 REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
115 // Reset dma
116 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
117 REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
118
119 // Set CPU back to XTAL source, no PLL, same as hard reset
120 #if !CONFIG_IDF_ENV_FPGA
121 rtc_clk_cpu_freq_set_xtal();
122 #endif
123
124 #if !CONFIG_FREERTOS_UNICORE
125 // Clear entry point for APP CPU
126 REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
127 #endif
128
129 // Reset CPUs
130 if (core_id == 0) {
131 // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
132 #if !CONFIG_FREERTOS_UNICORE
133 esp_cpu_reset(1);
134 #endif
135 esp_cpu_reset(0);
136 }
137 #if !CONFIG_FREERTOS_UNICORE
138 else {
139 // Running on APP CPU: need to reset PRO CPU and unstall it,
140 // then reset APP CPU
141 esp_cpu_reset(0);
142 esp_cpu_unstall(0);
143 esp_cpu_reset(1);
144 }
145 #endif
146 while (true) {
147 ;
148 }
149 }
150
