1 // Copyright 2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <string.h>
16 #include "sdkconfig.h"
17 #include "esp_system.h"
18 #include "esp_private/system_internal.h"
19 #include "esp_attr.h"
20 #include "esp_efuse.h"
21 #include "esp_log.h"
22 #include "esp32s2/rom/cache.h"
23 #include "esp_rom_uart.h"
24 #include "soc/dport_reg.h"
25 #include "soc/gpio_reg.h"
26 #include "soc/rtc_cntl_reg.h"
27 #include "soc/timer_group_reg.h"
28 #include "soc/cpu.h"
29 #include "soc/rtc.h"
30 #include "soc/syscon_reg.h"
31 #include "soc/rtc_periph.h"
32 #include "hal/wdt_hal.h"
33 #include "freertos/xtensa_api.h"
34 #include "hal/cpu_hal.h"
35
36 #include "esp32s2/rom/rtc.h"
37
38 /* "inner" restart function for after RTOS, interrupts & anything else on this
39 * core are already stopped. Stalls other core, resets hardware,
40 * triggers restart.
41 */
esp_restart_noos(void)42 void IRAM_ATTR esp_restart_noos(void)
43 {
44 // Disable interrupts
45 xt_ints_off(0xFFFFFFFF);
46
47 // Enable RTC watchdog for 1 second
48 wdt_hal_context_t rtc_wdt_ctx;
49 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
50 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
51 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
52 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
53 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
54 //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
55 wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
56 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
57
58 // Reset and stall the other CPU.
59 // CPU must be reset before stalling, in case it was running a s32c1i
60 // instruction. This would cause memory pool to be locked by arbiter
61 // to the stalled CPU, preventing current CPU from accessing this pool.
62 const uint32_t core_id = cpu_hal_get_core_id();
63
64 //Todo: Refactor to use Interrupt or Task Watchdog API, and a system level WDT context
65 // Disable TG0/TG1 watchdogs
66 wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
67 wdt_hal_write_protect_disable(&wdt0_context);
68 wdt_hal_disable(&wdt0_context);
69 wdt_hal_write_protect_enable(&wdt0_context);
70
71 wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
72 wdt_hal_write_protect_disable(&wdt1_context);
73 wdt_hal_disable(&wdt1_context);
74 wdt_hal_write_protect_enable(&wdt1_context);
75
76 // Flush any data left in UART FIFOs
77 esp_rom_uart_tx_wait_idle(0);
78 esp_rom_uart_tx_wait_idle(1);
79 // Disable cache
80 Cache_Disable_ICache();
81 Cache_Disable_DCache();
82
83 // 2nd stage bootloader reconfigures SPI flash signals.
84 // Reset them to the defaults expected by ROM.
85 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
86 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
87 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
88 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
89 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
90 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
91
92 // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
93 DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
94 DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
95 DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
96 DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
97 DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
98 DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
99
100 // Reset timer/spi/uart
101 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
102 DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI2_DMA_RST | DPORT_SPI3_DMA_RST | DPORT_UART_RST);
103 DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
104
105 // Set CPU back to XTAL source, no PLL, same as hard reset
106 rtc_clk_cpu_freq_set_xtal();
107
108 // Reset CPUs
109 if (core_id == 0) {
110 esp_cpu_reset(0);
111 }
112 while (true) {
113 ;
114 }
115 }
116
