Home
last modified time | relevance | path

Searched refs:levels (Results 1 – 25 of 33) sorted by relevance

12

/hal_espressif-3.4.0/components/log/
DREADME.rst11 - **At runtime**: all logs for verbosity levels lower than :ref:`CONFIG_LOG_DEFAULT_LEVEL` are enab…
13 There are the following verbosity levels:
23 …The function :cpp:func:`esp_log_level_set` cannot set logging levels higher than specified by :ref…
41 Several macros are available for different verbosity levels:
/hal_espressif-3.4.0/examples/wifi/ftm/main/
DKconfig.projbuild27 bool "Show RSSI levels"
/hal_espressif-3.4.0/docs/en/api-guides/
Dhlinterrupts.rst7 The Xtensa architecture has support for 32 interrupts, divided over 7 levels (levels 1 to 7, with 7…
Dlinker-script-generation.rst74 It is possible to specify placements at the following levels of granularity:
411 There are three levels of placement granularity:
Dhardware-abstraction.rst4 … are a group of API that allow users to control peripherals at differing levels of abstraction, as…
/hal_espressif-3.4.0/components/esp32c3/
DKconfig77 …#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
78 #of the brownout threshold levels.
/hal_espressif-3.4.0/components/esp32h2/
DKconfig73 …#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
74 #of the brownout threshold levels.
/hal_espressif-3.4.0/components/hal/
DREADME.md10 The abstraction design is actually two levels -- often somtimes `xxx_hal.h` includes a lower-level …
/hal_espressif-3.4.0/examples/storage/ext_flash_fatfs/
DREADME.md24 …ash chip connected to the ESP32. The SPI Flash chip must have 3.3V logic levels. The example has b…
/hal_espressif-3.4.0/docs/en/api-reference/
Dtemplate.rst28 …3. To distinguish between sections, use the following `heading levels <http://www.sphinx-doc.org/e…
/hal_espressif-3.4.0/components/esp32s2/
DKconfig277 …#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
278 #of the brownout threshold levels.
/hal_espressif-3.4.0/components/esp32s3/
DKconfig349 …#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
350 #of the brownout threshold levels.
/hal_espressif-3.4.0/tools/
Didf_tools.py392 def strip_container_dirs(path, levels): # type: (str, int) -> None argument
393 assert levels > 0
402 for level in range(levels):
/hal_espressif-3.4.0/docs/en/api-reference/protocols/
Dmqtt.rst15 …hing, authentication, last will messages, keep alive pings and all 3 QoS levels (it should be a fu…
/hal_espressif-3.4.0/
D.pylintrc50 # Only show warnings with the listed confidence levels. Leave empty to show
51 # all. Valid levels: HIGH, INFERENCE, INFERENCE_FAILURE, UNDEFINED.
DKconfig230 Note that custom optimization levels may be unsupported.
/hal_espressif-3.4.0/docs/en/api-reference/peripherals/
Dledc.rst169 …ere from 0 to 100% with a resolution of ~0.012% (2 ** 13 = 8192 discrete levels of the LED intensi…
/hal_espressif-3.4.0/docs/en/api-guides/performance/
Dspeed.rst147 ESP-IDF starts a number of system tasks at fixed priority levels. Some are automatically started du…
151 Header :idf_file:`components/esp_system/include/esp_task.h` contains macros for the priority levels…
/hal_espressif-3.4.0/docs/en/api-reference/provisioning/
Dprovisioning.rst73 There are two levels of security schemes. The developer may select one or combination depending on …
/hal_espressif-3.4.0/docs/en/api-reference/system/
Dheap_debug.rst92 …debugging``. The setting :ref:`CONFIG_HEAP_CORRUPTION_DETECTION` can be set to one of three levels:
451 …in the heap leak trace if the data was received/transmitted by the lower levels of the network whi…
/hal_espressif-3.4.0/components/esp32/
DKconfig551 …#The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
552 #of the brownout threshold levels.
/hal_espressif-3.4.0/docs/en/get-started-legacy/
Dindex.rst298 … ``CHIP_PU`` (EN) pins of {IDF_TARGET_NAME}, thus changes in the voltage levels of DTR and RTS wil…
/hal_espressif-3.4.0/docs/en/api-guides/jtag-debugging/
Dindex.rst96 …rate JTAG adapter, look for one that is compatible with both the voltage levels on the {IDF_TARGET…
/hal_espressif-3.4.0/components/esptool_py/esptool/docs/en/advanced-topics/
Dboot-mode-selection.rst118 …N`` (``CHIP_PU``) pins of {IDF_TARGET_NAME}, thus changes in the voltage levels of ``DTR`` and ``R…
/hal_espressif-3.4.0/components/freertos/port/xtensa/
Dreadme_xtensa.txt619 Medium priority interrupts are those at levels 2 up to XCHAL_EXCM_LEVEL,
622 Interrupt levels above XCHAL_EXCM_LEVEL are of the high-priority class.

12