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Searched refs:RoReg16 (Results 1 – 25 of 213) sorted by relevance

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/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dsdhc0.h111 #define REG_SDHC0_ACESR (*(RoReg16*)0x4500003CUL) /**< \brief (SDHC0) Auto CMD Error Sta…
128 #define REG_SDHC0_SISR (*(RoReg16*)0x450000FCUL) /**< \brief (SDHC0) Slot Interrupt Sta…
129 #define REG_SDHC0_HCVR (*(RoReg16*)0x450000FEUL) /**< \brief (SDHC0) Host Controller Ve…
Dsdhc1.h111 #define REG_SDHC1_ACESR (*(RoReg16*)0x4600003CUL) /**< \brief (SDHC1) Auto CMD Error Sta…
128 #define REG_SDHC1_SISR (*(RoReg16*)0x460000FCUL) /**< \brief (SDHC1) Slot Interrupt Sta…
129 #define REG_SDHC1_HCVR (*(RoReg16*)0x460000FEUL) /**< \brief (SDHC1) Host Controller Ve…
Ddac.h68 #define REG_DAC_RESULT0 (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */
69 #define REG_DAC_RESULT1 (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */
Dadc0.h81 #define REG_ADC0_RESULT (*(RoReg16*)0x43001C40UL) /**< \brief (ADC0) Result Conversion V…
82 #define REG_ADC0_RESS (*(RoReg16*)0x43001C44UL) /**< \brief (ADC0) Last Sample Result …
Dadc1.h81 #define REG_ADC1_RESULT (*(RoReg16*)0x43002040UL) /**< \brief (ADC1) Result Conversion V…
82 #define REG_ADC1_RESS (*(RoReg16*)0x43002044UL) /**< \brief (ADC1) Last Sample Result …
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dsdhc0.h111 #define REG_SDHC0_ACESR (*(RoReg16*)0x4500003CUL) /**< \brief (SDHC0) Auto CMD Error Sta…
128 #define REG_SDHC0_SISR (*(RoReg16*)0x450000FCUL) /**< \brief (SDHC0) Slot Interrupt Sta…
129 #define REG_SDHC0_HCVR (*(RoReg16*)0x450000FEUL) /**< \brief (SDHC0) Host Controller Ve…
Ddac.h68 #define REG_DAC_RESULT0 (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */
69 #define REG_DAC_RESULT1 (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */
Dadc0.h81 #define REG_ADC0_RESULT (*(RoReg16*)0x43001C40UL) /**< \brief (ADC0) Result Conversion V…
82 #define REG_ADC0_RESS (*(RoReg16*)0x43001C44UL) /**< \brief (ADC0) Last Sample Result …
/hal_atmel-latest/asf/sam0/include/same53/instance/
Dsdhc0.h111 #define REG_SDHC0_ACESR (*(RoReg16*)0x4500003CUL) /**< \brief (SDHC0) Auto CMD Error Sta…
128 #define REG_SDHC0_SISR (*(RoReg16*)0x450000FCUL) /**< \brief (SDHC0) Slot Interrupt Sta…
129 #define REG_SDHC0_HCVR (*(RoReg16*)0x450000FEUL) /**< \brief (SDHC0) Host Controller Ve…
Dsdhc1.h111 #define REG_SDHC1_ACESR (*(RoReg16*)0x4600003CUL) /**< \brief (SDHC1) Auto CMD Error Sta…
128 #define REG_SDHC1_SISR (*(RoReg16*)0x460000FCUL) /**< \brief (SDHC1) Slot Interrupt Sta…
129 #define REG_SDHC1_HCVR (*(RoReg16*)0x460000FEUL) /**< \brief (SDHC1) Host Controller Ve…
Ddac.h68 #define REG_DAC_RESULT0 (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */
69 #define REG_DAC_RESULT1 (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */
Dadc0.h81 #define REG_ADC0_RESULT (*(RoReg16*)0x43001C40UL) /**< \brief (ADC0) Result Conversion V…
82 #define REG_ADC0_RESS (*(RoReg16*)0x43001C44UL) /**< \brief (ADC0) Last Sample Result …
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dsdhc0.h111 #define REG_SDHC0_ACESR (*(RoReg16*)0x4500003CUL) /**< \brief (SDHC0) Auto CMD Error Sta…
128 #define REG_SDHC0_SISR (*(RoReg16*)0x450000FCUL) /**< \brief (SDHC0) Slot Interrupt Sta…
129 #define REG_SDHC0_HCVR (*(RoReg16*)0x450000FEUL) /**< \brief (SDHC0) Host Controller Ve…
Dsdhc1.h111 #define REG_SDHC1_ACESR (*(RoReg16*)0x4600003CUL) /**< \brief (SDHC1) Auto CMD Error Sta…
128 #define REG_SDHC1_SISR (*(RoReg16*)0x460000FCUL) /**< \brief (SDHC1) Slot Interrupt Sta…
129 #define REG_SDHC1_HCVR (*(RoReg16*)0x460000FEUL) /**< \brief (SDHC1) Host Controller Ve…
Ddac.h68 #define REG_DAC_RESULT0 (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */
69 #define REG_DAC_RESULT1 (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */
Dadc0.h81 #define REG_ADC0_RESULT (*(RoReg16*)0x43001C40UL) /**< \brief (ADC0) Result Conversion V…
82 #define REG_ADC0_RESS (*(RoReg16*)0x43001C44UL) /**< \brief (ADC0) Last Sample Result …
/hal_atmel-latest/asf/sam0/include/saml21/instance/
Dadc.h76 #define REG_ADC_SYNCBUSY (*(RoReg16*)0x43000C20UL) /**< \brief (ADC) Synchronization Busy…
77 #define REG_ADC_RESULT (*(RoReg16*)0x43000C24UL) /**< \brief (ADC) Result */
/hal_atmel-latest/asf/sam0/include/samr34/instance/
Dadc.h76 #define REG_ADC_SYNCBUSY (*(RoReg16*)0x43000C20UL) /**< \brief (ADC) Synchronization Busy…
77 #define REG_ADC_RESULT (*(RoReg16*)0x43000C24UL) /**< \brief (ADC) Result */
/hal_atmel-latest/asf/sam0/include/samr35/instance/
Dadc.h76 #define REG_ADC_SYNCBUSY (*(RoReg16*)0x43000C20UL) /**< \brief (ADC) Synchronization Busy…
77 #define REG_ADC_RESULT (*(RoReg16*)0x43000C24UL) /**< \brief (ADC) Result */
/hal_atmel-latest/asf/sam0/include/samc21n/instance/
Dadc0.h76 #define REG_ADC0_SYNCBUSY (*(RoReg16*)0x42004420UL) /**< \brief (ADC0) Synchronization Bus…
77 #define REG_ADC0_RESULT (*(RoReg16*)0x42004424UL) /**< \brief (ADC0) Result */
Dadc1.h76 #define REG_ADC1_SYNCBUSY (*(RoReg16*)0x42004820UL) /**< \brief (ADC1) Synchronization Bus…
77 #define REG_ADC1_RESULT (*(RoReg16*)0x42004824UL) /**< \brief (ADC1) Result */
/hal_atmel-latest/asf/sam0/include/samc20/instance/
Dadc0.h76 #define REG_ADC0_SYNCBUSY (*(RoReg16*)0x42004420UL) /**< \brief (ADC0) Synchronization Bus…
77 #define REG_ADC0_RESULT (*(RoReg16*)0x42004424UL) /**< \brief (ADC0) Result */
/hal_atmel-latest/asf/sam0/include/samc20n/instance/
Dadc0.h76 #define REG_ADC0_SYNCBUSY (*(RoReg16*)0x42004420UL) /**< \brief (ADC0) Synchronization Bus…
77 #define REG_ADC0_RESULT (*(RoReg16*)0x42004424UL) /**< \brief (ADC0) Result */
/hal_atmel-latest/asf/sam0/include/samc21/instance/
Dadc0.h76 #define REG_ADC0_SYNCBUSY (*(RoReg16*)0x42004420UL) /**< \brief (ADC0) Synchronization Bus…
77 #define REG_ADC0_RESULT (*(RoReg16*)0x42004424UL) /**< \brief (ADC0) Result */
Dadc1.h76 #define REG_ADC1_SYNCBUSY (*(RoReg16*)0x42004820UL) /**< \brief (ADC1) Synchronization Bus…
77 #define REG_ADC1_RESULT (*(RoReg16*)0x42004824UL) /**< \brief (ADC1) Result */

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