1 /** 2 * \file 3 * 4 * \brief Instance description for ADC0 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC20_ADC0_INSTANCE_ 31 #define _SAMC20_ADC0_INSTANCE_ 32 33 /* ========== Register definition for ADC0 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_ADC0_CTRLA (0x42004400) /**< \brief (ADC0) Control A */ 36 #define REG_ADC0_CTRLB (0x42004401) /**< \brief (ADC0) Control B */ 37 #define REG_ADC0_REFCTRL (0x42004402) /**< \brief (ADC0) Reference Control */ 38 #define REG_ADC0_EVCTRL (0x42004403) /**< \brief (ADC0) Event Control */ 39 #define REG_ADC0_INTENCLR (0x42004404) /**< \brief (ADC0) Interrupt Enable Clear */ 40 #define REG_ADC0_INTENSET (0x42004405) /**< \brief (ADC0) Interrupt Enable Set */ 41 #define REG_ADC0_INTFLAG (0x42004406) /**< \brief (ADC0) Interrupt Flag Status and Clear */ 42 #define REG_ADC0_SEQSTATUS (0x42004407) /**< \brief (ADC0) Sequence Status */ 43 #define REG_ADC0_INPUTCTRL (0x42004408) /**< \brief (ADC0) Input Control */ 44 #define REG_ADC0_CTRLC (0x4200440A) /**< \brief (ADC0) Control C */ 45 #define REG_ADC0_AVGCTRL (0x4200440C) /**< \brief (ADC0) Average Control */ 46 #define REG_ADC0_SAMPCTRL (0x4200440D) /**< \brief (ADC0) Sample Time Control */ 47 #define REG_ADC0_WINLT (0x4200440E) /**< \brief (ADC0) Window Monitor Lower Threshold */ 48 #define REG_ADC0_WINUT (0x42004410) /**< \brief (ADC0) Window Monitor Upper Threshold */ 49 #define REG_ADC0_GAINCORR (0x42004412) /**< \brief (ADC0) Gain Correction */ 50 #define REG_ADC0_OFFSETCORR (0x42004414) /**< \brief (ADC0) Offset Correction */ 51 #define REG_ADC0_SWTRIG (0x42004418) /**< \brief (ADC0) Software Trigger */ 52 #define REG_ADC0_DBGCTRL (0x4200441C) /**< \brief (ADC0) Debug Control */ 53 #define REG_ADC0_SYNCBUSY (0x42004420) /**< \brief (ADC0) Synchronization Busy */ 54 #define REG_ADC0_RESULT (0x42004424) /**< \brief (ADC0) Result */ 55 #define REG_ADC0_SEQCTRL (0x42004428) /**< \brief (ADC0) Sequence Control */ 56 #define REG_ADC0_CALIB (0x4200442C) /**< \brief (ADC0) Calibration */ 57 #else 58 #define REG_ADC0_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (ADC0) Control A */ 59 #define REG_ADC0_CTRLB (*(RwReg8 *)0x42004401UL) /**< \brief (ADC0) Control B */ 60 #define REG_ADC0_REFCTRL (*(RwReg8 *)0x42004402UL) /**< \brief (ADC0) Reference Control */ 61 #define REG_ADC0_EVCTRL (*(RwReg8 *)0x42004403UL) /**< \brief (ADC0) Event Control */ 62 #define REG_ADC0_INTENCLR (*(RwReg8 *)0x42004404UL) /**< \brief (ADC0) Interrupt Enable Clear */ 63 #define REG_ADC0_INTENSET (*(RwReg8 *)0x42004405UL) /**< \brief (ADC0) Interrupt Enable Set */ 64 #define REG_ADC0_INTFLAG (*(RwReg8 *)0x42004406UL) /**< \brief (ADC0) Interrupt Flag Status and Clear */ 65 #define REG_ADC0_SEQSTATUS (*(RoReg8 *)0x42004407UL) /**< \brief (ADC0) Sequence Status */ 66 #define REG_ADC0_INPUTCTRL (*(RwReg16*)0x42004408UL) /**< \brief (ADC0) Input Control */ 67 #define REG_ADC0_CTRLC (*(RwReg16*)0x4200440AUL) /**< \brief (ADC0) Control C */ 68 #define REG_ADC0_AVGCTRL (*(RwReg8 *)0x4200440CUL) /**< \brief (ADC0) Average Control */ 69 #define REG_ADC0_SAMPCTRL (*(RwReg8 *)0x4200440DUL) /**< \brief (ADC0) Sample Time Control */ 70 #define REG_ADC0_WINLT (*(RwReg16*)0x4200440EUL) /**< \brief (ADC0) Window Monitor Lower Threshold */ 71 #define REG_ADC0_WINUT (*(RwReg16*)0x42004410UL) /**< \brief (ADC0) Window Monitor Upper Threshold */ 72 #define REG_ADC0_GAINCORR (*(RwReg16*)0x42004412UL) /**< \brief (ADC0) Gain Correction */ 73 #define REG_ADC0_OFFSETCORR (*(RwReg16*)0x42004414UL) /**< \brief (ADC0) Offset Correction */ 74 #define REG_ADC0_SWTRIG (*(RwReg8 *)0x42004418UL) /**< \brief (ADC0) Software Trigger */ 75 #define REG_ADC0_DBGCTRL (*(RwReg8 *)0x4200441CUL) /**< \brief (ADC0) Debug Control */ 76 #define REG_ADC0_SYNCBUSY (*(RoReg16*)0x42004420UL) /**< \brief (ADC0) Synchronization Busy */ 77 #define REG_ADC0_RESULT (*(RoReg16*)0x42004424UL) /**< \brief (ADC0) Result */ 78 #define REG_ADC0_SEQCTRL (*(RwReg *)0x42004428UL) /**< \brief (ADC0) Sequence Control */ 79 #define REG_ADC0_CALIB (*(RwReg16*)0x4200442CUL) /**< \brief (ADC0) Calibration */ 80 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 82 /* ========== Instance parameters for ADC0 peripheral ========== */ 83 #define ADC0_DMAC_ID_RESRDY 42 // index of DMA RESRDY trigger 84 #define ADC0_EXTCHANNEL_MSB 11 // Number of external channels 85 #define ADC0_GCLK_ID 33 // index of Generic Clock 86 #define ADC0_INT_CH30 0 // Select OPAMP or CTAT on Channel 30 87 #define ADC0_MASTER_SLAVE_MODE 1 // ADC Master/Slave Mode 88 89 #endif /* _SAMC20_ADC0_INSTANCE_ */ 90
