1 /** 2 * \file 3 * 4 * \brief Instance description for ADC1 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_ADC1_INSTANCE_ 31 #define _SAMC21_ADC1_INSTANCE_ 32 33 /* ========== Register definition for ADC1 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_ADC1_CTRLA (0x42004800) /**< \brief (ADC1) Control A */ 36 #define REG_ADC1_CTRLB (0x42004801) /**< \brief (ADC1) Control B */ 37 #define REG_ADC1_REFCTRL (0x42004802) /**< \brief (ADC1) Reference Control */ 38 #define REG_ADC1_EVCTRL (0x42004803) /**< \brief (ADC1) Event Control */ 39 #define REG_ADC1_INTENCLR (0x42004804) /**< \brief (ADC1) Interrupt Enable Clear */ 40 #define REG_ADC1_INTENSET (0x42004805) /**< \brief (ADC1) Interrupt Enable Set */ 41 #define REG_ADC1_INTFLAG (0x42004806) /**< \brief (ADC1) Interrupt Flag Status and Clear */ 42 #define REG_ADC1_SEQSTATUS (0x42004807) /**< \brief (ADC1) Sequence Status */ 43 #define REG_ADC1_INPUTCTRL (0x42004808) /**< \brief (ADC1) Input Control */ 44 #define REG_ADC1_CTRLC (0x4200480A) /**< \brief (ADC1) Control C */ 45 #define REG_ADC1_AVGCTRL (0x4200480C) /**< \brief (ADC1) Average Control */ 46 #define REG_ADC1_SAMPCTRL (0x4200480D) /**< \brief (ADC1) Sample Time Control */ 47 #define REG_ADC1_WINLT (0x4200480E) /**< \brief (ADC1) Window Monitor Lower Threshold */ 48 #define REG_ADC1_WINUT (0x42004810) /**< \brief (ADC1) Window Monitor Upper Threshold */ 49 #define REG_ADC1_GAINCORR (0x42004812) /**< \brief (ADC1) Gain Correction */ 50 #define REG_ADC1_OFFSETCORR (0x42004814) /**< \brief (ADC1) Offset Correction */ 51 #define REG_ADC1_SWTRIG (0x42004818) /**< \brief (ADC1) Software Trigger */ 52 #define REG_ADC1_DBGCTRL (0x4200481C) /**< \brief (ADC1) Debug Control */ 53 #define REG_ADC1_SYNCBUSY (0x42004820) /**< \brief (ADC1) Synchronization Busy */ 54 #define REG_ADC1_RESULT (0x42004824) /**< \brief (ADC1) Result */ 55 #define REG_ADC1_SEQCTRL (0x42004828) /**< \brief (ADC1) Sequence Control */ 56 #define REG_ADC1_CALIB (0x4200482C) /**< \brief (ADC1) Calibration */ 57 #else 58 #define REG_ADC1_CTRLA (*(RwReg8 *)0x42004800UL) /**< \brief (ADC1) Control A */ 59 #define REG_ADC1_CTRLB (*(RwReg8 *)0x42004801UL) /**< \brief (ADC1) Control B */ 60 #define REG_ADC1_REFCTRL (*(RwReg8 *)0x42004802UL) /**< \brief (ADC1) Reference Control */ 61 #define REG_ADC1_EVCTRL (*(RwReg8 *)0x42004803UL) /**< \brief (ADC1) Event Control */ 62 #define REG_ADC1_INTENCLR (*(RwReg8 *)0x42004804UL) /**< \brief (ADC1) Interrupt Enable Clear */ 63 #define REG_ADC1_INTENSET (*(RwReg8 *)0x42004805UL) /**< \brief (ADC1) Interrupt Enable Set */ 64 #define REG_ADC1_INTFLAG (*(RwReg8 *)0x42004806UL) /**< \brief (ADC1) Interrupt Flag Status and Clear */ 65 #define REG_ADC1_SEQSTATUS (*(RoReg8 *)0x42004807UL) /**< \brief (ADC1) Sequence Status */ 66 #define REG_ADC1_INPUTCTRL (*(RwReg16*)0x42004808UL) /**< \brief (ADC1) Input Control */ 67 #define REG_ADC1_CTRLC (*(RwReg16*)0x4200480AUL) /**< \brief (ADC1) Control C */ 68 #define REG_ADC1_AVGCTRL (*(RwReg8 *)0x4200480CUL) /**< \brief (ADC1) Average Control */ 69 #define REG_ADC1_SAMPCTRL (*(RwReg8 *)0x4200480DUL) /**< \brief (ADC1) Sample Time Control */ 70 #define REG_ADC1_WINLT (*(RwReg16*)0x4200480EUL) /**< \brief (ADC1) Window Monitor Lower Threshold */ 71 #define REG_ADC1_WINUT (*(RwReg16*)0x42004810UL) /**< \brief (ADC1) Window Monitor Upper Threshold */ 72 #define REG_ADC1_GAINCORR (*(RwReg16*)0x42004812UL) /**< \brief (ADC1) Gain Correction */ 73 #define REG_ADC1_OFFSETCORR (*(RwReg16*)0x42004814UL) /**< \brief (ADC1) Offset Correction */ 74 #define REG_ADC1_SWTRIG (*(RwReg8 *)0x42004818UL) /**< \brief (ADC1) Software Trigger */ 75 #define REG_ADC1_DBGCTRL (*(RwReg8 *)0x4200481CUL) /**< \brief (ADC1) Debug Control */ 76 #define REG_ADC1_SYNCBUSY (*(RoReg16*)0x42004820UL) /**< \brief (ADC1) Synchronization Busy */ 77 #define REG_ADC1_RESULT (*(RoReg16*)0x42004824UL) /**< \brief (ADC1) Result */ 78 #define REG_ADC1_SEQCTRL (*(RwReg *)0x42004828UL) /**< \brief (ADC1) Sequence Control */ 79 #define REG_ADC1_CALIB (*(RwReg16*)0x4200482CUL) /**< \brief (ADC1) Calibration */ 80 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 82 /* ========== Instance parameters for ADC1 peripheral ========== */ 83 #define ADC1_DMAC_ID_RESRDY 43 // index of DMA RESRDY trigger 84 #define ADC1_EXTCHANNEL_MSB 11 // Number of external channels 85 #define ADC1_GCLK_ID 34 // index of Generic Clock 86 #define ADC1_INT_CH30 0 // Select OPAMP or CTAT on Channel 30 87 #define ADC1_MASTER_SLAVE_MODE 2 // ADC Master/Slave Mode 88 89 #endif /* _SAMC21_ADC1_INSTANCE_ */ 90
