Searched refs:RoReg (Results 1 – 25 of 752) sorted by relevance
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149 #define REG_GMAC_NSR (*(RoReg *)0x42000808UL) /**< \brief (GMAC) Network Status Regi…159 #define REG_GMAC_IMR (*(RoReg *)0x42000830UL) /**< \brief (GMAC) Interrupt Mask Regi…161 #define REG_GMAC_RPQ (*(RoReg *)0x42000838UL) /**< \brief (GMAC) Received Pause Quan…189 #define REG_GMAC_EFTSH (*(RoReg *)0x420008E8UL) /**< \brief (GMAC) PTP Event Frame Tra…190 #define REG_GMAC_EFRSH (*(RoReg *)0x420008ECUL) /**< \brief (GMAC) PTP Event Frame Rec…191 #define REG_GMAC_PEFTSH (*(RoReg *)0x420008F0UL) /**< \brief (GMAC) PTP Peer Event Fram…192 #define REG_GMAC_PEFRSH (*(RoReg *)0x420008F4UL) /**< \brief (GMAC) PTP Peer Event Fram…193 #define REG_GMAC_OTLO (*(RoReg *)0x42000900UL) /**< \brief (GMAC) Octets Transmitted …194 #define REG_GMAC_OTHI (*(RoReg *)0x42000904UL) /**< \brief (GMAC) Octets Transmitted …195 #define REG_GMAC_FT (*(RoReg *)0x42000908UL) /**< \brief (GMAC) Frames Transmitted …[all …]
70 #define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identificatio…72 #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table …73 #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table …74 #define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table …75 #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table …76 #define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identific…77 #define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identific…78 #define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identific…79 #define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identific…80 #define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identific…[all …]
129 #define REG_GMAC_NSR (*(RoReg*)0x40034008U) /**< \brief (GMAC) Network Status Register */136 #define REG_GMAC_ISR (*(RoReg*)0x40034024U) /**< \brief (GMAC) Interrupt Status Register */139 #define REG_GMAC_IMR (*(RoReg*)0x40034030U) /**< \brief (GMAC) Interrupt Mask Register */141 #define REG_GMAC_RPQ (*(RoReg*)0x40034038U) /**< \brief (GMAC) Received Pause Quantum Registe…159 #define REG_GMAC_OTLO (*(RoReg*)0x40034100U) /**< \brief (GMAC) Octets Transmitted [31:0] Regi…160 #define REG_GMAC_OTHI (*(RoReg*)0x40034104U) /**< \brief (GMAC) Octets Transmitted [47:32] Reg…161 #define REG_GMAC_FT (*(RoReg*)0x40034108U) /**< \brief (GMAC) Frames Transmitted Register */162 #define REG_GMAC_BCFT (*(RoReg*)0x4003410CU) /**< \brief (GMAC) Broadcast Frames Transmitted R…163 #define REG_GMAC_MFT (*(RoReg*)0x40034110U) /**< \brief (GMAC) Multicast Frames Transmitted R…164 #define REG_GMAC_PFT (*(RoReg*)0x40034114U) /**< \brief (GMAC) Pause Frames Transmitted Regis…[all …]
248 #define REG_PDCA_SR0 (*(RoReg *)0x400A201CUL) /**< \brief (PDCA) Status Register 0 */251 #define REG_PDCA_IMR0 (*(RoReg *)0x400A2028UL) /**< \brief (PDCA) Interrupt Mask Regi…252 #define REG_PDCA_ISR0 (*(RoReg *)0x400A202CUL) /**< \brief (PDCA) Interrupt Status Re…260 #define REG_PDCA_SR1 (*(RoReg *)0x400A205CUL) /**< \brief (PDCA) Status Register 1 */263 #define REG_PDCA_IMR1 (*(RoReg *)0x400A2068UL) /**< \brief (PDCA) Interrupt Mask Regi…264 #define REG_PDCA_ISR1 (*(RoReg *)0x400A206CUL) /**< \brief (PDCA) Interrupt Status Re…272 #define REG_PDCA_SR2 (*(RoReg *)0x400A209CUL) /**< \brief (PDCA) Status Register 2 */275 #define REG_PDCA_IMR2 (*(RoReg *)0x400A20A8UL) /**< \brief (PDCA) Interrupt Mask Regi…276 #define REG_PDCA_ISR2 (*(RoReg *)0x400A20ACUL) /**< \brief (PDCA) Interrupt Status Re…284 #define REG_PDCA_SR3 (*(RoReg *)0x400A20DCUL) /**< \brief (PDCA) Status Register 3 */[all …]
186 #define REG_USBC_UDINT (*(RoReg *)0x400A5004UL) /**< \brief (USBC) Device Global Inter…189 #define REG_USBC_UDINTE (*(RoReg *)0x400A5010UL) /**< \brief (USBC) Device Global Inter…193 #define REG_USBC_UDFNUM (*(RoReg *)0x400A5020UL) /**< \brief (USBC) Device Frame Number…202 #define REG_USBC_UESTA0 (*(RoReg *)0x400A5130UL) /**< \brief (USBC) Endpoint Status Reg…203 #define REG_USBC_UESTA1 (*(RoReg *)0x400A5134UL) /**< \brief (USBC) Endpoint Status Reg…204 #define REG_USBC_UESTA2 (*(RoReg *)0x400A5138UL) /**< \brief (USBC) Endpoint Status Reg…205 #define REG_USBC_UESTA3 (*(RoReg *)0x400A513CUL) /**< \brief (USBC) Endpoint Status Reg…206 #define REG_USBC_UESTA4 (*(RoReg *)0x400A5140UL) /**< \brief (USBC) Endpoint Status Reg…207 #define REG_USBC_UESTA5 (*(RoReg *)0x400A5144UL) /**< \brief (USBC) Endpoint Status Reg…208 #define REG_USBC_UESTA6 (*(RoReg *)0x400A5148UL) /**< \brief (USBC) Endpoint Status Reg…[all …]
50 RoReg GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */57 RoReg GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */60 RoReg GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */62 RoReg GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */64 RoReg Reserved1[16];69 RoReg Reserved2[1];75 RoReg Reserved3[12];76 RoReg GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted [31:0] Register */77 RoReg GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted [47:32] Register */78 RoReg GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */[all …]
64 #define REG_MTB_BASE (*(RoReg *)0x4100600CUL) /**< \brief (MTB) MTB Base */69 #define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4UL) /**< \brief (MTB) MTB Lock Status */70 #define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8UL) /**< \brief (MTB) MTB Authentication S…71 #define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCUL) /**< \brief (MTB) MTB Device Architect…72 #define REG_MTB_DEVID (*(RoReg *)0x41006FC8UL) /**< \brief (MTB) MTB Device Configura…73 #define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCUL) /**< \brief (MTB) MTB Device Type */74 #define REG_MTB_PID4 (*(RoReg *)0x41006FD0UL) /**< \brief (MTB) Peripheral Identific…75 #define REG_MTB_PID5 (*(RoReg *)0x41006FD4UL) /**< \brief (MTB) Peripheral Identific…76 #define REG_MTB_PID6 (*(RoReg *)0x41006FD8UL) /**< \brief (MTB) Peripheral Identific…77 #define REG_MTB_PID7 (*(RoReg *)0x41006FDCUL) /**< \brief (MTB) Peripheral Identific…[all …]
71 #define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identificatio…74 #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) Coresight ROM Table …75 #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) Coresight ROM Table …76 #define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) Coresight ROM Table …77 #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) Coresight ROM Table …78 #define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identific…79 #define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identific…80 #define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identific…81 #define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identific…82 #define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identific…[all …]
63 #define REG_MTB_BASE (*(RoReg *)0x4100600CUL) /**< \brief (MTB) MTB Base */68 #define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4UL) /**< \brief (MTB) MTB Lock Status */69 #define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8UL) /**< \brief (MTB) MTB Authentication S…70 #define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCUL) /**< \brief (MTB) MTB Device Architect…71 #define REG_MTB_DEVID (*(RoReg *)0x41006FC8UL) /**< \brief (MTB) MTB Device Configura…72 #define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCUL) /**< \brief (MTB) MTB Device Type */73 #define REG_MTB_PID4 (*(RoReg *)0x41006FD0UL) /**< \brief (MTB) CoreSight */74 #define REG_MTB_PID5 (*(RoReg *)0x41006FD4UL) /**< \brief (MTB) CoreSight */75 #define REG_MTB_PID6 (*(RoReg *)0x41006FD8UL) /**< \brief (MTB) CoreSight */76 #define REG_MTB_PID7 (*(RoReg *)0x41006FDCUL) /**< \brief (MTB) CoreSight */[all …]
64 #define REG_MTB_BASE (*(RoReg *)0x4100800CUL) /**< \brief (MTB) MTB Base */69 #define REG_MTB_LOCKSTATUS (*(RoReg *)0x41008FB4UL) /**< \brief (MTB) MTB Lock Status */70 #define REG_MTB_AUTHSTATUS (*(RoReg *)0x41008FB8UL) /**< \brief (MTB) MTB Authentication S…71 #define REG_MTB_DEVARCH (*(RoReg *)0x41008FBCUL) /**< \brief (MTB) MTB Device Architect…72 #define REG_MTB_DEVID (*(RoReg *)0x41008FC8UL) /**< \brief (MTB) MTB Device Configura…73 #define REG_MTB_DEVTYPE (*(RoReg *)0x41008FCCUL) /**< \brief (MTB) MTB Device Type */74 #define REG_MTB_PID4 (*(RoReg *)0x41008FD0UL) /**< \brief (MTB) Peripheral Identific…75 #define REG_MTB_PID5 (*(RoReg *)0x41008FD4UL) /**< \brief (MTB) Peripheral Identific…76 #define REG_MTB_PID6 (*(RoReg *)0x41008FD8UL) /**< \brief (MTB) Peripheral Identific…77 #define REG_MTB_PID7 (*(RoReg *)0x41008FDCUL) /**< \brief (MTB) Peripheral Identific…[all …]
71 #define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identificatio…74 #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table …75 #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table …76 #define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table …77 #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table …78 #define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identific…79 #define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identific…80 #define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identific…81 #define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identific…82 #define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identific…[all …]
